d19332ca3a
While we are at it, also reflow a few lines that fit in 96 characters. Tested with BUILD_TIMELESS=1, Getac P470 does not change. Change-Id: I2cc3e71723e9b6898e6ec29f0f38b1b3b7446f09 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
224 lines
6.6 KiB
C
224 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ops.h>
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#include <device/pci_ids.h>
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#include "chip.h"
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#include "i82801gx.h"
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#include "sata.h"
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static u8 get_ich7_sata_ports(void)
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{
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struct device *lpc;
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lpc = pcidev_on_root(31, 0);
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switch (pci_read_config16(lpc, PCI_DEVICE_ID)) {
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case 0x27b0:
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case 0x27b8:
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return 0xf;
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case 0x27b9:
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case 0x27bd:
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return 0x5;
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case 0x27bc:
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return 0x3;
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default:
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printk(BIOS_ERR, "i82801gx_sata: error: cannot determine port config\n");
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return 0;
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}
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}
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void sata_enable(struct device *dev)
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{
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/* Get the chip configuration */
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struct southbridge_intel_i82801gx_config *config = dev->chip_info;
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if (config->sata_mode == SATA_MODE_AHCI) {
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/* Check if the southbridge supports AHCI */
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struct device *lpc_dev = pcidev_on_root(31, 0);
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if (!lpc_dev) {
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/* According to the PCI spec function 0 on a bus:device
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needs to be active for other functions to be enabled.
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Since SATA is on the same bus:device as the LPC
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bridge, it makes little sense to continue. */
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die("Couldn't find the LPC device!\n");
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}
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const bool ahci_supported = !(pci_read_config32(lpc_dev, FDVCT)
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& AHCI_UNSUPPORTED);
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if (!ahci_supported) {
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/* Fallback to IDE PLAIN for sata for the rest of the initialization */
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config->sata_mode = SATA_MODE_IDE_PLAIN;
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printk(BIOS_DEBUG, "AHCI not supported, falling back to plain mode.\n");
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}
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}
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if (config->sata_mode == SATA_MODE_AHCI) {
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/* Set map to ahci */
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pci_update_config8(dev, SATA_MAP, (u8)~0xc3, 0x40);
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} else {
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/* Set map to ide */
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pci_and_config8(dev, SATA_MAP, (u8)~0xc3);
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}
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/* At this point, the new pci id will appear on the bus */
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}
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static void sata_init(struct device *dev)
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{
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u32 reg32;
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u8 ports;
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/* Get the chip configuration */
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const struct southbridge_intel_i82801gx_config *config = dev->chip_info;
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printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n");
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if (config == NULL) {
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printk(BIOS_ERR, "i82801gx_sata: error: device not in devicetree.cb!\n");
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return;
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}
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/* Get ICH7 SATA port config */
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ports = get_ich7_sata_ports();
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/* Enable BARs */
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pci_write_config16(dev, PCI_COMMAND,
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PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
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switch (config->sata_mode) {
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case SATA_MODE_IDE_LEGACY_COMBINED:
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printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
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/* No AHCI: clear AHCI base */
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pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0);
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/* And without AHCI BAR no memory decoding */
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pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY);
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pci_write_config8(dev, 0x09, 0x80);
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/* Set timings */
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pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
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IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
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pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
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IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
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IDE_PPE0 | IDE_IE0 | IDE_TIME0);
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/* Sync DMA */
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pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
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pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
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/* Set IDE I/O Configuration */
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reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
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pci_write_config32(dev, IDE_CONFIG, reg32);
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/* Combine IDE - SATA configuration */
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pci_write_config8(dev, SATA_MAP, 0x02);
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/* Restrict ports - 0 and 2 only available */
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ports &= 0x5;
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break;
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case SATA_MODE_AHCI:
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printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
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/* Allow both Legacy and Native mode */
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pci_write_config8(dev, 0x09, 0x8f);
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/* Set Interrupt Line */
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/* Interrupt Pin is set by D31IP.PIP */
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pci_write_config8(dev, INTR_LN, 0x0a);
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struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5);
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if (ahci_res != NULL)
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/* write AHCI GHC_PI register */
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write32(res2mmio(ahci_res, 0xc, 0), config->sata_ports_implemented);
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break;
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default:
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case SATA_MODE_IDE_PLAIN:
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printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
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/* Set Sata Controller Mode. No Mapping(?) */
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pci_write_config8(dev, SATA_MAP, 0x00);
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/* No AHCI: clear AHCI base */
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pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000);
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/* And without AHCI BAR no memory decoding */
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pci_and_config16(dev, PCI_COMMAND, ~PCI_COMMAND_MEMORY);
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/* Native mode capable on both primary and secondary (0xa)
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* or'ed with enabled (0x50) = 0xf
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*/
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pci_write_config8(dev, 0x09, 0x8f);
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/* Set Interrupt Line */
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/* Interrupt Pin is set by D31IP.PIP */
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pci_write_config8(dev, INTR_LN, 0xff);
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/* Set timings */
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pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
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IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
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IDE_PPE0 | IDE_IE0 | IDE_TIME0);
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pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
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IDE_SITRE | IDE_ISP_3_CLOCKS |
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IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
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/* Sync DMA */
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pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
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pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
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/* Set IDE I/O Configuration */
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reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
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pci_write_config32(dev, IDE_CONFIG, reg32);
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break;
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}
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/* Set port control */
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pci_write_config8(dev, SATA_PCS, ports);
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/* Enable clock gating for unused ports and set initialization reg */
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pci_write_config32(dev, SATA_IR, SIF3(ports) | SIF2 | SIF1 | SCRE);
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/* All configurations need this SATA initialization sequence */
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pci_write_config8(dev, 0xa0, 0x40);
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pci_write_config8(dev, 0xa6, 0x22);
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pci_write_config8(dev, 0xa0, 0x78);
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pci_write_config8(dev, 0xa6, 0x22);
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pci_write_config8(dev, 0xa0, 0x88);
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pci_update_config32(dev, 0xa4, 0xc0c0c0c0, 0x1b1b1212);
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pci_write_config8(dev, 0xa0, 0x8c);
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pci_update_config32(dev, 0xa4, 0xc0c0ff00, 0x121200aa);
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pci_write_config8(dev, 0xa0, 0x00);
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pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
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/* Sata Initialization Register */
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pci_or_config32(dev, SATA_IR, SCRD); // due to some bug
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}
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static struct device_operations sata_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = sata_init,
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.enable = i82801gx_enable,
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.ops_pci = &pci_dev_ops_pci,
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};
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static const unsigned short sata_ids[] = {
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0x27c0, /* Desktop Non-AHCI and Non-RAID Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
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0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
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0x27c4, /* Mobile Non-AHCI and Non-RAID Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
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0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */
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/* NOTE: Any of the below are not properly supported yet. */
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0x27c3, /* Desktop RAID mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */
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0x27c6, /* ICH7M DH Raid Mode: 82801GHM (ICH7-M DH) */
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0
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};
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static const struct pci_driver i82801gx_sata_driver __pci_driver = {
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.ops = &sata_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.devices = sata_ids,
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};
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