06ef889718
Change-Id: I53ed687dc49524e001889f091825b2cc530546a3 Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/19492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
40 lines
1.3 KiB
C
40 lines
1.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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* Copyright (C) 2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/pci.h>
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#include <intelblocks/uart.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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static int pch_uart_is_debug(struct device *dev)
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{
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return dev->path.pci.devfn == PCH_DEVFN_UART2;
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}
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void pch_uart_read_resources(struct device *dev)
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{
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pci_dev_read_resources(dev);
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/* Set the configured UART base address for the debug port */
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if (IS_ENABLED(CONFIG_UART_DEBUG) && pch_uart_is_debug(dev)) {
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struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
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/* Need to set the base and size for the resource allocator. */
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res->base = UART_DEBUG_BASE_ADDRESS;
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res->size = UART_DEBUG_BASE_SIZE;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
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IORESOURCE_FIXED;
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}
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}
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