cd2afc0df0
Instead of defining the same functions for reading/clearing boot-mode switches from EC in every mainboard, add a common infrastructure to enable common functions for handling boot-mode switches if GOOGLE_CHROMEEC is being used. Only boards that were not moved to this new infrastructure are those that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific mechanism for reading boot-mode switches. BUG=None BRANCH=None TEST=abuild compiles all boards successfully with and without ChromeOS option. Change-Id: I267aadea9e616464563df04b51a668b877f0d578 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17449 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner <jwerner@chromium.org>
84 lines
2.8 KiB
C
84 lines
2.8 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <string.h>
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#include <bootmode.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#ifndef __PRE_RAM__
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#include <boot/coreboot_tables.h>
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#define GPIO_COUNT 6
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void fill_lb_gpios(struct lb_gpios *gpios)
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{
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gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
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gpios->count = GPIO_COUNT;
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/* Write Protect: GPIO57 = PCH_SPI_WP_D */
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gpios->gpios[0].port = 57;
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gpios->gpios[0].polarity = ACTIVE_HIGH;
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gpios->gpios[0].value = get_write_protect_state();
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strncpy((char *)gpios->gpios[0].name,"write protect",
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GPIO_MAX_NAME_LENGTH);
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/* Recovery: the "switch" comes from the EC */
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gpios->gpios[1].port = -1; /* Indicate that this is a pseudo GPIO */
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gpios->gpios[1].polarity = ACTIVE_HIGH;
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gpios->gpios[1].value = get_recovery_mode_switch();
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strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
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/* Lid: the "switch" comes from the EC */
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gpios->gpios[2].port = -1;
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gpios->gpios[2].polarity = ACTIVE_HIGH;
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gpios->gpios[2].value = get_lid_switch();
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strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH);
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/* Power Button: hard-coded as not pressed; we'll detect later presses
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* via SMI. */
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gpios->gpios[3].port = -1;
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gpios->gpios[3].polarity = ACTIVE_HIGH;
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gpios->gpios[3].value = 0;
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strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH);
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/* Developer: a tricky case on Link, there is no switch */
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gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */
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gpios->gpios[4].polarity = ACTIVE_HIGH;
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gpios->gpios[4].value = get_developer_mode_switch();
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strncpy((char *)gpios->gpios[4].name,"developer", GPIO_MAX_NAME_LENGTH);
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/* Did we load the VGA Option ROM? */
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gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
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gpios->gpios[5].polarity = ACTIVE_HIGH;
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gpios->gpios[5].value = gfx_get_init_done();
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strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
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}
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#endif
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int get_write_protect_state(void)
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{
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return get_gpio(57);
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}
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static const struct cros_gpio cros_gpios[] = {
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CROS_GPIO_REC_AL(9, CROS_GPIO_DEVICE_NAME),
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CROS_GPIO_WP_AH(57, CROS_GPIO_DEVICE_NAME),
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};
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void mainboard_chromeos_acpi_generate(void)
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{
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chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
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}
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