59493717ad
gcc doesn't like these because they're undefined behavior, so use zeroptr instead. For the loop that just does a number of writes (0..4), use zeroptr + i. Checked the disassembly (AMD_RUMBA and PCENGINES_ALIX2D) to not contain ud2 anymore and to look reasonable where zeroptr was used. Change-Id: I4a58220ec9a10c465909ca4ecbe5366d0a8cc0df Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14345 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
606 lines
18 KiB
C
606 lines
18 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Advanced Micro Devices, Inc.
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* Copyright (C) 2010 Nils Jacobs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <cpu/amd/gx2def.h>
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#include <spd.h>
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#include <stddef.h>
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static const unsigned char NumColAddr[] = {
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0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
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0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
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};
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static void __attribute__((noreturn)) hcf(void)
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{
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printk(BIOS_EMERG, "DIE\n");
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/* this guarantees we flush the UART fifos (if any) and also
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* ensures that things, in general, keep going so no debug output
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* is lost
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*/
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while (1)
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printk(BIOS_EMERG, (0));
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}
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static void auto_size_dimm(unsigned int dimm)
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{
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uint32_t dimm_setting;
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uint16_t dimm_size;
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uint8_t spd_byte;
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msr_t msr;
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dimm_setting = 0;
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printk(BIOS_DEBUG, "Check present\n");
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/* Check that we have a dimm */
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if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
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return;
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}
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printk(BIOS_DEBUG, "MODBANKS\n");
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/* Field: Module Banks per DIMM */
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/* EEPROM byte usage: (5) Number of DIMM Banks */
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spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
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if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
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printk(BIOS_EMERG, "Number of module banks not compatible\n");
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post_code(ERROR_BANK_SET);
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hcf();
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}
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dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
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printk(BIOS_DEBUG, "FIELDBANKS\n");
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/* Field: Banks per SDRAM device */
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/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
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spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
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if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
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printk(BIOS_EMERG, "Number of device banks not compatible\n");
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post_code(ERROR_BANK_SET);
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hcf();
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}
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dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
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printk(BIOS_DEBUG, "SPDNUMROWS\n");
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/* Field: DIMM size
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* EEPROM byte usage:
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* (3) Number of Row Addresses
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* (4) Number of Column Addresses
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* (5) Number of DIMM Banks
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* (31) Module Bank Density
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* Size = Module Density * Module Banks
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*/
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if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
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|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
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printk(BIOS_EMERG, "Asymmetric DIMM not compatible\n");
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post_code(ERROR_UNSUPPORTED_DIMM);
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hcf();
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}
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printk(BIOS_DEBUG, "SPDBANKDENSITY\n");
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dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
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printk(BIOS_DEBUG, "DIMMSIZE\n");
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dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
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dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
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/* Module Density * Module Banks */
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dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
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printk(BIOS_DEBUG, "BEFORT CTZ\n");
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dimm_size = __builtin_ctz(dimm_size);
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printk(BIOS_DEBUG, "TEST DIMM SIZE>7\n");
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if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */
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printk(BIOS_EMERG, "Only support up to 512MB per DIMM\n");
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post_code(ERROR_DENSITY_DIMM);
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hcf();
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}
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dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
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printk(BIOS_DEBUG, "PAGESIZE\n");
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/*
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* Field: PAGE size
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* EEPROM byte usage: (4) Number of Column Addresses
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* PageSize = 2^# Column Addresses * Data width in bytes
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* (should be 8bytes for a normal DIMM)
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*
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* But this really works by magic.
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* If ma[11:0] is the memory address pins, and pa[13:0] is the physical column
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* address that MC generates, here is how the MC assigns the pa onto the
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* ma pins:
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*
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* ma 11 10 09 08 07 06 05 04 03 02 01 00
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* ---------------------------------------
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* pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size)
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* pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size)
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* pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size)
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* pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)
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* pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)
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*
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* (AP = autoprecharge bit)
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*
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* Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
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* so lower 3 address bits are dont_cares. So from the table above,
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* it's easier to see what the old code is doing: if for example,
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* #col_addr_bits=7(06h), it adds 3 to get 10, then does 2^10=1K.
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*/
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spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
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printk(BIOS_DEBUG, "MAXCOLADDR\n");
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if (spd_byte > MAX_COL_ADDR) {
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printk(BIOS_EMERG, "DIMM page size not compatible\n");
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post_code(ERROR_SET_PAGE);
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hcf();
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}
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printk(BIOS_DEBUG, ">11address test\n");
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spd_byte -= 7;
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if (spd_byte > 4) { /* if the value is above 4 it means >11 col address lines */
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spd_byte = 7; /* which means >16k so set to disabled */
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}
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dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0=1k,1=2k,2=4k,etc */
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printk(BIOS_DEBUG, "RDMSR CF07\n");
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msr = rdmsr(MC_CF07_DATA);
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printk(BIOS_DEBUG, "WRMSR CF07\n");
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if (dimm == DIMM0) {
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msr.hi &= 0xFFFF0000;
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msr.hi |= dimm_setting;
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} else {
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msr.hi &= 0x0000FFFF;
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msr.hi |= dimm_setting << 16;
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}
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wrmsr(MC_CF07_DATA, msr);
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printk(BIOS_DEBUG, "ALL DONE\n");
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}
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static void checkDDRMax(void)
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{
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uint8_t spd_byte0, spd_byte1;
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uint16_t speed;
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/* PC133 identifier */
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spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
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if (spd_byte0 == 0xFF) {
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spd_byte0 = 0;
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}
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spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
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if (spd_byte1 == 0xFF) {
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spd_byte1 = 0;
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}
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/* Use the slowest DIMM */
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if (spd_byte0 < spd_byte1) {
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spd_byte0 = spd_byte1;
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}
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/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
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speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));
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/* current speed > max speed? */
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if (GeodeLinkSpeed() > speed) {
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printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
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post_code(POST_PLL_MEM_FAIL);
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hcf();
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}
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}
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const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
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static void set_refresh_rate(void)
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{
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uint8_t spd_byte0, spd_byte1;
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uint16_t rate0, rate1;
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msr_t msr;
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spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);
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spd_byte0 &= 0xF;
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if (spd_byte0 > 5) {
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spd_byte0 = 5;
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}
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rate0 = REF_RATE[spd_byte0];
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spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);
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spd_byte1 &= 0xF;
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if (spd_byte1 > 5) {
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spd_byte1 = 5;
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}
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rate1 = REF_RATE[spd_byte1];
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/* Use the faster rate (lowest number) */
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if (rate0 > rate1) {
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rate0 = rate1;
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}
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msr = rdmsr(MC_CF07_DATA);
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msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
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<< CF07_LOWER_REF_INT_SHIFT;
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wrmsr(MC_CF07_DATA, msr);
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}
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const uint8_t CASDDR[] = { 5, 5, 2, 6, 0 }; /* 1(1.5), 1.5, 2, 2.5, 0 */
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static u8 getcasmap(u32 dimm, u16 glspeed)
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{
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u16 dimm_speed;
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u8 spd_byte, casmap, casmap_shift=0;
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/************************** DIMM0 **********************************/
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casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);
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if (casmap != 0xFF) {
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/* IF -.5 timing is supported, check -.5 timing > GeodeLink */
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spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);
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if (spd_byte != 0) {
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/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
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dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
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if (dimm_speed >= glspeed) {
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casmap_shift = 1; /* -.5 is a shift of 1 */
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/* IF -1 timing is supported, check -1 timing > GeodeLink */
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spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);
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if (spd_byte != 0) {
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/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
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dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
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if (dimm_speed >= glspeed) {
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casmap_shift = 2; /* -1 is a shift of 2 */
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}
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} /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
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} else {
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casmap_shift = 0;
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}
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} /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
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/* set the casmap based on the shift to limit possible CAS settings */
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spd_byte = 31 - __builtin_clz((uint32_t) casmap);
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/* just want bits in the lower byte since we have to cast to a 32 */
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casmap &= 0xFF << (spd_byte - casmap_shift);
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} else { /* No DIMM */
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casmap = 0;
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}
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return casmap;
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}
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static void setCAS(void)
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{
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/*
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* setCAS
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* EEPROM byte usage: (18) SDRAM device attributes - CAS latency
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* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
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* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
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*
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* The CAS setting is based on the information provided in each DIMMs SPD.
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* The speed at which a DIMM can run is described relative to the slowest
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* CAS the DIMM supports. Each speed for the relative CAS settings is
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* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
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* speed, the CAS setting is removed from the list of good settings for
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* the DIMM. This is done for both DIMMs and the lists are compared to
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* find the lowest common CAS latency setting. If there are no CAS settings
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* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
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*
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* Entry:
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* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
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* Destroys: We really use everything !
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*/
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uint16_t glspeed;
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uint8_t spd_byte, casmap0, casmap1;
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msr_t msr;
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glspeed = GeodeLinkSpeed();
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casmap0 = getcasmap(DIMM0, glspeed);
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casmap1 = getcasmap(DIMM1, glspeed);
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/* CAS_LAT MAP COMPARE */
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if (casmap0 == 0) {
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spd_byte = CASDDR[__builtin_ctz(casmap1)];
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} else if (casmap1 == 0) {
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spd_byte = CASDDR[__builtin_ctz(casmap0)];
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} else if ((casmap0 &= casmap1)) {
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spd_byte = CASDDR[__builtin_ctz(casmap0)];
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} else {
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printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");
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post_code(ERROR_DIFF_DIMMS);
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hcf();
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}
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msr = rdmsr(MC_CF8F_DATA);
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msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
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msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;
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wrmsr(MC_CF8F_DATA, msr);
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}
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static void set_latencies(void)
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{
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uint32_t memspeed, dimm_setting;
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uint8_t spd_byte0, spd_byte1;
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msr_t msr;
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memspeed = GeodeLinkSpeed() / 2;
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dimm_setting = 0;
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/* MC_CF8F setup */
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/* tRAS */
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spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);
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if (spd_byte0 == 0xFF) {
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spd_byte0 = 0;
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}
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spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);
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if (spd_byte1 == 0xFF) {
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spd_byte1 = 0;
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}
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if (spd_byte0 < spd_byte1) {
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spd_byte0 = spd_byte1;
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}
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/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
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spd_byte1 = (spd_byte0 * memspeed) / 1000;
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if (((spd_byte0 * memspeed) % 1000)) {
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++spd_byte1;
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}
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if (spd_byte1 > 6) {
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--spd_byte1;
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}
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dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
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/* tRP */
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spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);
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if (spd_byte0 == 0xFF) {
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spd_byte0 = 0;
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}
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spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);
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if (spd_byte1 == 0xFF) {
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spd_byte1 = 0;
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}
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if (spd_byte0 < spd_byte1) {
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spd_byte0 = spd_byte1;
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}
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/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
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spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
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if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
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++spd_byte1;
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}
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dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
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/* tRCD */
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spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);
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if (spd_byte0 == 0xFF) {
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spd_byte0 = 0;
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}
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spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);
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if (spd_byte1 == 0xFF) {
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spd_byte1 = 0;
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}
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if (spd_byte0 < spd_byte1) {
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spd_byte0 = spd_byte1;
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}
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/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
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spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
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if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
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++spd_byte1;
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}
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dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
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/* tRRD */
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spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);
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if (spd_byte0 == 0xFF) {
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spd_byte0 = 0;
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}
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spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);
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if (spd_byte1 == 0xFF) {
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spd_byte1 = 0;
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}
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if (spd_byte0 < spd_byte1) {
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spd_byte0 = spd_byte1;
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}
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/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
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spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
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if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
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++spd_byte1;
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}
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dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
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/* tRC = tRP + tRAS */
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dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
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((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
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<< CF8F_LOWER_REF2ACT_SHIFT;
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msr = rdmsr(MC_CF8F_DATA);
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msr.lo &= 0xF00000FF;
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msr.lo |= dimm_setting;
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msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
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wrmsr(MC_CF8F_DATA, msr);
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printk(BIOS_DEBUG, "MSR MC_CF8F_DATA (%08x) value is %08x:%08x\n",
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|
MC_CF8F_DATA, msr.hi, msr.lo);
|
|
}
|
|
|
|
static void set_extended_mode_registers(void)
|
|
{
|
|
uint8_t spd_byte0, spd_byte1;
|
|
msr_t msr;
|
|
spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);
|
|
if (spd_byte0 == 0xFF) {
|
|
spd_byte0 = 0;
|
|
}
|
|
spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);
|
|
if (spd_byte1 == 0xFF) {
|
|
spd_byte1 = 0;
|
|
}
|
|
spd_byte1 &= spd_byte0;
|
|
|
|
msr = rdmsr(MC_CF07_DATA);
|
|
if (spd_byte1 & 1) { /* Drive Strength Control */
|
|
msr.lo |= CF07_LOWER_EMR_DRV_SET;
|
|
}
|
|
if (spd_byte1 & 2) { /* FET Control */
|
|
msr.lo |= CF07_LOWER_EMR_QFC_SET;
|
|
}
|
|
wrmsr(MC_CF07_DATA, msr);
|
|
}
|
|
|
|
static void sdram_set_registers(const struct mem_controller *ctrl)
|
|
{
|
|
msr_t msr;
|
|
uint32_t msrnum;
|
|
|
|
/* Set Refresh Staggering */
|
|
msrnum = MC_CF07_DATA;
|
|
msr = rdmsr(msrnum);
|
|
msr.lo &= ~0xC0;
|
|
msr.lo |= 0x0; /* set refresh to 4SDRAM clocks */
|
|
wrmsr(msrnum, msr);
|
|
}
|
|
|
|
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
|
|
{
|
|
uint8_t spd_byte;
|
|
|
|
printk(BIOS_DEBUG, "sdram_set_spd_register\n");
|
|
post_code(POST_MEM_SETUP); /* post_70h */
|
|
|
|
spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
|
|
printk(BIOS_DEBUG, "Check DIMM 0\n");
|
|
/* Check DIMM is not Register and not Buffered DIMMs. */
|
|
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
|
|
printk(BIOS_EMERG, "DIMM0 NOT COMPATIBLE\n");
|
|
post_code(ERROR_UNSUPPORTED_DIMM);
|
|
hcf();
|
|
}
|
|
printk(BIOS_DEBUG, "Check DIMM 1\n");
|
|
spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
|
|
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
|
|
printk(BIOS_EMERG, "DIMM1 NOT COMPATIBLE\n");
|
|
post_code(ERROR_UNSUPPORTED_DIMM);
|
|
hcf();
|
|
}
|
|
|
|
post_code(POST_MEM_SETUP2); /* post_72h */
|
|
printk(BIOS_DEBUG, "Check DDR MAX\n");
|
|
|
|
/* Check that the memory is not overclocked. */
|
|
checkDDRMax();
|
|
|
|
/* Size the DIMMS */
|
|
post_code(POST_MEM_SETUP3); /* post_73h */
|
|
printk(BIOS_DEBUG, "AUTOSIZE DIMM 0\n");
|
|
auto_size_dimm(DIMM0);
|
|
post_code(POST_MEM_SETUP4); /* post_74h */
|
|
printk(BIOS_DEBUG, "AUTOSIZE DIMM 1\n");
|
|
auto_size_dimm(DIMM1);
|
|
|
|
/* Set CAS latency */
|
|
printk(BIOS_DEBUG, "set cas latency\n");
|
|
post_code(POST_MEM_SETUP5); /* post_75h */
|
|
setCAS();
|
|
|
|
/* Set all the other latencies here (tRAS, tRP....) */
|
|
printk(BIOS_DEBUG, "set all latency\n");
|
|
set_latencies();
|
|
|
|
/* Set Extended Mode Registers */
|
|
printk(BIOS_DEBUG, "set emrs\n");
|
|
set_extended_mode_registers();
|
|
|
|
printk(BIOS_DEBUG, "set ref rate\n");
|
|
/* Set Memory Refresh Rate */
|
|
set_refresh_rate();
|
|
}
|
|
|
|
/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
|
|
* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
|
|
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
|
|
{
|
|
int i;
|
|
msr_t msr;
|
|
|
|
/* 2. clock gating for PMode */
|
|
msr = rdmsr(MC_GLD_MSR_PM);
|
|
msr.lo &= ~0x04;
|
|
msr.lo |= 0x01;
|
|
wrmsr(MC_GLD_MSR_PM, msr);
|
|
/* undocmented bits in GX, in LX there are
|
|
* 8 bits in PM1_UP_DLY */
|
|
msr = rdmsr(MC_CF1017_DATA);
|
|
msr.lo = 0x0101;
|
|
wrmsr(MC_CF1017_DATA, msr);
|
|
printk(BIOS_DEBUG, "sdram_enable step 2\n");
|
|
|
|
/* 3. release CKE mask to enable CKE */
|
|
msr = rdmsr(MC_CFCLK_DBUG);
|
|
msr.lo &= ~(0x03 << 8);
|
|
wrmsr(MC_CFCLK_DBUG, msr);
|
|
printk(BIOS_DEBUG, "sdram_enable step 3\n");
|
|
|
|
/* 4. set and clear REF_TST 16 times, more shouldn't hurt
|
|
* why this is before EMRS and MRS ? */
|
|
for (i = 0; i < 19; i++) {
|
|
msr = rdmsr(MC_CF07_DATA);
|
|
msr.lo |= (0x01 << 3);
|
|
wrmsr(MC_CF07_DATA, msr);
|
|
msr.lo &= ~(0x01 << 3);
|
|
wrmsr(MC_CF07_DATA, msr);
|
|
}
|
|
printk(BIOS_DEBUG, "sdram_enable step 4\n");
|
|
|
|
/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
|
|
msr = rdmsr(MC_CF07_DATA);
|
|
msr.lo |= ((0x01 << 28) | 0x01);
|
|
wrmsr(MC_CF07_DATA, msr);
|
|
msr.lo &= ~((0x01 << 28) | 0x01);
|
|
wrmsr(MC_CF07_DATA, msr);
|
|
printk(BIOS_DEBUG, "sdram_enable step 6\n");
|
|
|
|
/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
|
|
* it is documented in LX datasheet */
|
|
/* load Mode Register by set and clear PROG_DRAM */
|
|
msr = rdmsr(MC_CF07_DATA);
|
|
msr.lo |= ((0x01 << 27) | 0x01);
|
|
wrmsr(MC_CF07_DATA, msr);
|
|
msr.lo &= ~((0x01 << 27) | 0x01);
|
|
wrmsr(MC_CF07_DATA, msr);
|
|
printk(BIOS_DEBUG, "sdram_enable step 7\n");
|
|
|
|
/* 8. load Mode Register by set and clear PROG_DRAM */
|
|
msr = rdmsr(MC_CF07_DATA);
|
|
msr.lo |= 0x01;
|
|
wrmsr(MC_CF07_DATA, msr);
|
|
msr.lo &= ~0x01;
|
|
wrmsr(MC_CF07_DATA, msr);
|
|
printk(BIOS_DEBUG, "sdram_enable step 8\n");
|
|
|
|
/* wait 200 SDCLKs */
|
|
for (i = 0; i < 200; i++)
|
|
outb(0xaa, 0x80);
|
|
|
|
/* load RDSYNC */
|
|
msr = rdmsr(MC_CF_RDSYNC);
|
|
msr.hi = 0x000ff310;
|
|
/* the above setting is supposed to be good for "slow" ram. We have found that for
|
|
* some dram, at some clock rates, e.g. hynix at 366/244, this will actually
|
|
* cause errors. The fix is to just set it to 0x310. Tested on 3 boards
|
|
* with 3 different type of dram -- Hynix, PSC, infineon.
|
|
* I am leaving this comment here so that at some future time nobody is tempted
|
|
* to mess with this setting -- RGM, 9/2006
|
|
*/
|
|
msr.hi = 0x00000310;
|
|
msr.lo = 0x00000000;
|
|
wrmsr(MC_CF_RDSYNC, msr);
|
|
|
|
/* set delay control */
|
|
msr = rdmsr(GLCP_DELAY_CONTROLS);
|
|
msr.hi = 0x830d415a;
|
|
msr.lo = 0x8ea0ad6a;
|
|
wrmsr(GLCP_DELAY_CONTROLS, msr);
|
|
|
|
/* The RAM dll needs a write to lock on so generate a few dummy writes */
|
|
/* Note: The descriptor needs to be enabled to point at memory */
|
|
for (i = 0; i < 5; i++) {
|
|
write32(zeroptr + i, i);
|
|
}
|
|
|
|
printk(BIOS_INFO, "RAM DLL lock\n");
|
|
|
|
}
|