Subrata Banik 85c9dda1c4 soc/intel/alderlake/romstage: Refactor soc_memory_init_params function ... This patch create separate helper functions to fill-in required FSP-M UPDs as per IP initialization categories. This would help to increase the code readability and in future meaningful addition of FSP-M UPDs is possible rather adding UPDs randomly. TEST=FSP-M UPD dump shows no change without and with this code change. Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55225 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2021-06-17 05:43:11 +00:00
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amd	timestamp,amd/common/apob_cache: Add timestamps for APOB	2021-06-16 22:42:05 +00:00
cavium
example
intel	soc/intel/alderlake/romstage: Refactor soc_memory_init_params function	2021-06-17 05:43:11 +00:00
mediatek	soc/mediatek/mt8195: Add ddp driver to support eDP output	2021-06-16 08:32:31 +00:00
nvidia
qualcomm	sc7280: Add target specific GPIO pin definitions	2021-06-11 07:36:16 +00:00
rockchip
samsung	commonlib/region: Turn addrspace_32bit into a more official API	2021-04-21 02:06:26 +00:00
sifive
ti	soc/ti/am335x/mmc.c: Fix memset length argument	2021-04-04 09:58:26 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00