e95b6b291e
Change-Id: I0c0058be002e409bd16d2d75fd404df94407df4e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/19348 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
69 lines
1.5 KiB
Text
69 lines
1.5 KiB
Text
#
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# This file is part of the coreboot project.
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#
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# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; version 2 of the License.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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config NORTHBRIDGE_AMD_PI
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bool
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default y if CPU_AMD_PI
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default n
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select CBMEM_TOP_BACKUP
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select RELOCATABLE_RAMSTAGE
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if NORTHBRIDGE_AMD_PI
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config BOTTOMIO_POSITION
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hex "Bottom of 32-bit IO space"
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default 0xD0000000
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help
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If PCI peripherals with big BARs are connected to the system
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the bottom of the IO must be decreased to allocate such
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devices.
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Declare the beginning of the 128MB-aligned MMIO region. This
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option is useful when PCI peripherals requesting large address
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ranges are present.
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config CONSOLE_VGA_MULTI
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bool
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default n
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config S3_VGA_ROM_RUN
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bool
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default n
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source src/northbridge/amd/pi/00630F01/Kconfig
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source src/northbridge/amd/pi/00730F01/Kconfig
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source src/northbridge/amd/pi/00660F01/Kconfig
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config HW_MEM_HOLE_SIZEK
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hex
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default 0x200000
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config HW_MEM_HOLE_SIZE_AUTO_INC
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bool
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default n
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config RAMTOP
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hex
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default 0x1000000
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config HEAP_SIZE
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hex
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default 0xc0000
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config RAMBASE
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hex
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default 0x200000
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endif # NORTHBRIDGE_AMD_PI
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