eaa9c4596b
We've had gpiolib.h which defines a few common GPIO access functions for a while, but it wasn't really complete. This patch adds the missing gpio_output() function, and also renames the unwieldy gpio_get_in_value() and gpio_set_out_value() to the much easier to handle gpio_get() and gpio_set(). The header is renamed to the simpler gpio.h while we're at it (there was never really anything "lib" about it, and it was presumably just chosen due to the IPQ806x include/ conflict problem that is now resolved). It also moves the definition of gpio_t into SoC-specific code, so that different implementations are free to encode their platform-specific GPIO parameters in those 4 bytes in the most convenient way (such as the rk3288 with a bitfield struct). Every SoC intending to use this common API should supply a <soc/gpio.h> that typedefs gpio_t to a type at most 4 bytes in length. Files accessing the API only need to include <gpio.h> which may pull in additional things (like a gpio_t creation macro) from <soc/gpio.h> on its own. For now the API is still only used on non-x86 SoCs. Whether it makes sense to expand it to x86 as well should be separately evaluated at a later point (by someone who understands those systems better). Also, Exynos retains its old, incompatible GPIO API even though it would be a prime candidate, because it's currently just not worth the effort. BUG=None TEST=Compiled on Daisy, Peach_Pit, Nyan_Blaze, Rush_Ryu, Storm and Veyron_Pinky. Change-Id: Ieee77373c2bd13d07ece26fa7f8b08be324842fe Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9e04902ada56b929e3829f2c3b4aeb618682096e Original-Change-Id: I6c1e7d1e154d9b02288aabedb397e21e1aadfa15 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/220975 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/9400 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
103 lines
3 KiB
C
103 lines
3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <gpio.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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#include <soc/early_configs.h>
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#include <soc/nvidia/tegra/i2c.h>
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static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
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static void setup_pinmux(void)
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{
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/* Write protect. */
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gpio_input_pullup(GPIO(R1));
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/* Recovery mode. */
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gpio_input_pullup(GPIO(Q7));
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/* Lid switch. */
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gpio_input_pullup(GPIO(R4));
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/* Power switch. */
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gpio_input_pullup(GPIO(Q0));
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/* Developer mode. */
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gpio_input_pullup(GPIO(Q6));
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/* EC in RW. */
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gpio_input_pullup(GPIO(U4));
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/* route PU4/5 to GMI to remove conflict w/PWM1/2. */
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pinmux_set_config(PINMUX_GPIO_PU4_INDEX,
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PINMUX_GPIO_PU4_FUNC_NOR); /* s/b GMI */
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pinmux_set_config(PINMUX_GPIO_PU5_INDEX,
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PINMUX_GPIO_PU5_FUNC_NOR); /* s/b GMI */
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/* SOC and TPM reset GPIO, active low. */
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gpio_output(GPIO(I5), 1);
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/* SPI1 MOSI */
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pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
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PINMUX_PULL_NONE |
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PINMUX_INPUT_ENABLE);
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/* SPI1 MISO */
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pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
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PINMUX_PULL_NONE |
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PINMUX_INPUT_ENABLE);
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/* SPI1 SCLK */
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pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
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PINMUX_PULL_NONE |
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PINMUX_INPUT_ENABLE);
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/* SPI1 CS0 */
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pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
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PINMUX_PULL_NONE |
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PINMUX_INPUT_ENABLE);
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/* I2C3 (cam) clock. */
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pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
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PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
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/* I2C3 (cam) data. */
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pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
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PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
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/* switch unused pin to GPIO */
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gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO);
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gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO);
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gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO);
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gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO);
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gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO);
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gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO);
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}
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static void configure_ec_spi_bus(void)
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{
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clock_configure_source(sbc1, CLK_M, 3000);
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}
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static void configure_tpm_i2c_bus(void)
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{
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clock_configure_i2c_scl_freq(i2c3, PLLP, 400);
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i2c_init(2);
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}
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void early_mainboard_init(void)
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{
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clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0);
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setup_pinmux();
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configure_ec_spi_bus();
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configure_tpm_i2c_bus();
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}
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