coreboot-kgpe-d16/src/northbridge/intel/gm45
Elyes HAOUAS 00b5f53361 treewide [Kconfig]: Remove useless comment
Change-Id: I3dafffa61f4fe6089fd11ef6579626aff8088df5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-02 13:49:49 +00:00
..
acpi nb/intel/gm45: Define and use MMCONF_BUS_NUMBER 2021-01-30 23:12:54 +00:00
acpi.c nb/intel/gm45: Define and use MMCONF_BUS_NUMBER 2021-01-30 23:12:54 +00:00
bootblock.c nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h> 2021-02-01 08:59:10 +00:00
chip.h
early_init.c nb/intel/gm45: Clean up header handling 2020-10-24 20:42:32 +00:00
early_reset.c
gm45.h nb/intel/gm45: Define and use MMCONF_BUS_NUMBER 2021-01-30 23:12:54 +00:00
gma.c
igd.c
iommu.c
Kconfig treewide [Kconfig]: Remove useless comment 2021-02-02 13:49:49 +00:00
Makefile.inc
memmap.c
memmap.h nb/intel/gm45: Introduce memmap.h 2020-10-24 20:42:19 +00:00
northbridge.c nb/intel/gm45: Define and use MMCONF_BUS_NUMBER 2021-01-30 23:12:54 +00:00
pcie.c nb/intel/gm45: Clean up header handling 2020-10-24 20:42:32 +00:00
pm.c
raminit.c nb/intel/gm45: Add more DMIBAR/EPBAR registers 2020-10-24 20:42:07 +00:00
raminit_rcomp_calibration.c
raminit_read_write_training.c
raminit_receive_enable_calibration.c
romstage.c
thermal.c