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Uwe Poeche 868c8074b5 sb/intel/common/spi: Increase flash erase timeout
This patch provides an increased timeout (60ms -> 1s) for SPI
HW-sequencing flash erase operations. Without that the erase for MRC
cache writing on siemens/mc_bdx1 sometimes goes wrong because the
timeout stops waiting for flash cycle completion. It was found
during continuous integration. Investigation showed that the used flash
type takes sporadic (e.g. 5% of the test cycles) more time for completion
of erasing operation if the ambient temperature increases. The measured
time values are in range of data sheet of SPI flash. 60ms is a typical
value. So increasing the value is necessary.

tested on siemens/bdx1; measured time values with increased ambient
temperature of flash were always smaller than worst case value of 1s.

Change-Id: Id50636f9ed834ffd7810946798b300e58b2c14d2
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2019-07-23 15:49:09 +00:00
3rdparty 3rdparty/fsp: Update submodule pointer 2019-07-02 16:11:03 +00:00
Documentation Documentation: Add 4.10/4.11 release notes 2019-07-22 23:33:57 +00:00
configs configs/lenovo: Drop DEBUG_SMM_RELOCATION 2019-07-15 04:49:09 +00:00
payloads vboot: deprecate vboot_handoff structure 2019-07-23 12:07:07 +00:00
src sb/intel/common/spi: Increase flash erase timeout 2019-07-23 15:49:09 +00:00
util util/*/Makefile: Rename -W to -Wextra 2019-07-23 09:10:47 +00:00
.checkpatch.conf .checkpatch.conf: Ignore a few more warnings 2018-08-13 12:23:24 +00:00
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.gitignore util/bucts: Add tool to manipulate BUC.TS bit on Intel targets 2018-11-19 08:19:16 +00:00
.gitmodules Add intel-microcode submodule repository 2019-06-18 10:42:17 +00:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: Add Portwell M107 maintainers 2019-07-21 18:58:48 +00:00
Makefile site-local: Allow to read Makefile.inc w/o .config 2019-07-17 16:05:04 +00:00
Makefile.inc Makefile.inc: Enable -Wimplicit-fallthrough 2019-07-19 09:58:05 +00:00
README.md README: Convert to Markdown 2018-09-16 13:01:58 +00:00
gnat.adc
toolchain.inc Move -Wlogical-op into xcompile 2019-06-21 08:44:49 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.