86d2afb86b
FSP-S is currently configuring GPIOs that it should not. This results in issues where mainboard devices don't behave as expected e.g. host unable to receive TPM interrupts as the pad for the interrupt is re-configured as something else. Until FSP-S is fixed, this change adds a workaround by reconfiguring GPIOs after FSP-S is run. All mainboards need to call cnl_configure_pads instead of gpio_configure_pads so that SoC code can maintain a reference to the GPIO table and use that to re-configure GPIOs after FSP-S is run. BUG=b:123721147 BRANCH=None TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch. Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/31250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
224 lines
6.4 KiB
C
224 lines
6.4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016-2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <chip.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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#include <intelblocks/acpi.h>
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#include <intelblocks/chip.h>
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#include <intelblocks/itss.h>
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#include <intelblocks/xdci.h>
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#include <romstage_handoff.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/itss.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <string.h>
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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const char *soc_acpi_name(const struct device *dev)
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{
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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return "PCI0";
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if (dev->path.type == DEVICE_PATH_USB) {
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switch (dev->path.usb.port_type) {
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case 0:
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/* Root Hub */
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return "RHUB";
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case 2:
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/* USB2 ports */
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switch (dev->path.usb.port_id) {
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case 0: return "HS01";
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case 1: return "HS02";
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case 2: return "HS03";
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case 3: return "HS04";
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case 4: return "HS05";
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case 5: return "HS06";
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case 6: return "HS07";
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case 7: return "HS08";
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case 8: return "HS09";
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case 9: return "HS10";
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case 10: return "HS11";
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case 11: return "HS12";
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}
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break;
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case 3:
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/* USB3 ports */
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switch (dev->path.usb.port_id) {
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case 0: return "SS01";
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case 1: return "SS02";
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case 2: return "SS03";
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case 3: return "SS04";
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case 4: return "SS05";
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case 5: return "SS06";
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}
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break;
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}
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return NULL;
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}
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if (dev->path.type != DEVICE_PATH_PCI)
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return NULL;
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switch (dev->path.pci.devfn) {
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case SA_DEVFN_ROOT: return "MCHC";
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case SA_DEVFN_IGD: return "GFX0";
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case PCH_DEVFN_ISH: return "ISHB";
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case PCH_DEVFN_XHCI: return "XHCI";
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case PCH_DEVFN_USBOTG: return "XDCI";
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case PCH_DEVFN_THERMAL: return "THRM";
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case PCH_DEVFN_I2C0: return "I2C0";
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case PCH_DEVFN_I2C1: return "I2C1";
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case PCH_DEVFN_I2C2: return "I2C2";
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case PCH_DEVFN_I2C3: return "I2C3";
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case PCH_DEVFN_CSE: return "CSE1";
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case PCH_DEVFN_CSE_2: return "CSE2";
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case PCH_DEVFN_CSE_IDER: return "CSED";
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case PCH_DEVFN_CSE_KT: return "CSKT";
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case PCH_DEVFN_CSE_3: return "CSE3";
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case PCH_DEVFN_SATA: return "SATA";
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case PCH_DEVFN_UART2: return "UAR2";
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case PCH_DEVFN_I2C4: return "I2C4";
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case PCH_DEVFN_I2C5: return "I2C5";
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case PCH_DEVFN_PCIE1: return "RP01";
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case PCH_DEVFN_PCIE2: return "RP02";
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case PCH_DEVFN_PCIE3: return "RP03";
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case PCH_DEVFN_PCIE4: return "RP04";
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case PCH_DEVFN_PCIE5: return "RP05";
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case PCH_DEVFN_PCIE6: return "RP06";
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case PCH_DEVFN_PCIE7: return "RP07";
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case PCH_DEVFN_PCIE8: return "RP08";
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case PCH_DEVFN_PCIE9: return "RP09";
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case PCH_DEVFN_PCIE10: return "RP10";
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case PCH_DEVFN_PCIE11: return "RP11";
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case PCH_DEVFN_PCIE12: return "RP12";
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case PCH_DEVFN_PCIE13: return "RP13";
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case PCH_DEVFN_PCIE14: return "RP14";
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case PCH_DEVFN_PCIE15: return "RP15";
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case PCH_DEVFN_PCIE16: return "RP16";
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case PCH_DEVFN_PCIE17: return "RP17";
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case PCH_DEVFN_PCIE18: return "RP18";
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case PCH_DEVFN_PCIE19: return "RP19";
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case PCH_DEVFN_PCIE20: return "RP20";
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case PCH_DEVFN_PCIE21: return "RP21";
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case PCH_DEVFN_PCIE22: return "RP22";
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case PCH_DEVFN_PCIE23: return "RP23";
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case PCH_DEVFN_PCIE24: return "RP24";
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case PCH_DEVFN_UART0: return "UAR0";
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case PCH_DEVFN_UART1: return "UAR1";
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case PCH_DEVFN_GSPI0: return "SPI0";
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case PCH_DEVFN_GSPI1: return "SPI1";
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case PCH_DEVFN_GSPI2: return "SPI2";
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case PCH_DEVFN_EMMC: return "EMMC";
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case PCH_DEVFN_SDCARD: return "SDXC";
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case PCH_DEVFN_LPC: return "LPCB";
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case PCH_DEVFN_P2SB: return "P2SB";
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case PCH_DEVFN_PMC: return "PMC_";
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case PCH_DEVFN_HDA: return "HDAS";
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case PCH_DEVFN_SMBUS: return "SBUS";
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case PCH_DEVFN_SPI: return "FSPI";
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case PCH_DEVFN_GBE: return "IGBE";
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case PCH_DEVFN_TRACEHUB:return "THUB";
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}
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return NULL;
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}
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#endif
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/*
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* TODO(furquan): Get rid of this workaround once FSP is fixed. Currently, FSP-S
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* configures GPIOs when it should not and this results in coreboot GPIO
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* configuration being overwritten. Until FSP is fixed, maintain the reference
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* of GPIO config table from mainboard and use that to re-configure GPIOs after
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* FSP-S is done.
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*/
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void cnl_configure_pads(const struct pad_config *cfg, size_t num_pads)
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{
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static const struct pad_config *g_cfg;
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static size_t g_num_pads;
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/*
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* If cfg and num_pads are passed in from mainboard, maintain a
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* reference to the GPIO table.
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*/
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if ((cfg == NULL) || (num_pads == 0)) {
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cfg = g_cfg;
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num_pads = g_num_pads;
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} else {
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g_cfg = cfg;
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g_num_pads = num_pads;
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}
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gpio_configure_pads(cfg, num_pads);
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}
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void soc_init_pre_device(void *chip_info)
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{
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/* Snapshot the current GPIO IRQ polarities. FSP is setting a
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* default policy that doesn't honor boards' requirements. */
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itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
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/* Perform silicon specific init. */
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fsp_silicon_init(romstage_handoff_is_resume());
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/* Display FIRMWARE_VERSION_INFO_HOB */
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fsp_display_fvi_version_hob();
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/* Restore GPIO IRQ polarities back to previous settings. */
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itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
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/* TODO(furquan): Get rid of this workaround once FSP is fixed. */
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cnl_configure_pads(NULL, 0);
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}
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static void pci_domain_set_resources(struct device *dev)
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{
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assign_resources(dev->link_list);
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}
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static struct device_operations pci_domain_ops = {
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.read_resources = &pci_domain_read_resources,
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.set_resources = &pci_domain_set_resources,
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.scan_bus = &pci_domain_scan_bus,
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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.acpi_name = &soc_acpi_name,
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#endif
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};
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static struct device_operations cpu_bus_ops = {
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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.enable_resources = DEVICE_NOOP,
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.init = DEVICE_NOOP,
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.acpi_fill_ssdt_generator = generate_cpu_entries,
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};
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static void soc_enable(struct device *dev)
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{
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/* Set the operations if it is a special bus type */
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if (dev->path.type == DEVICE_PATH_DOMAIN)
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dev->ops = &pci_domain_ops;
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else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
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dev->ops = &cpu_bus_ops;
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}
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struct chip_operations soc_intel_cannonlake_ops = {
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CHIP_NAME("Intel Cannonlake")
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.enable_dev = &soc_enable,
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.init = &soc_init_pre_device,
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};
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