a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
84 lines
2.3 KiB
C
84 lines
2.3 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <soc/addressmap.h>
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#include <soc/clk_rst.h>
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#include <soc/cpu.h>
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#include <soc/pmc.h>
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#define EVP_CPU_RESET_VECTOR (void *)(uintptr_t)(TEGRA_EVP_BASE + 0x100)
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#define PMC_REGS (void *)(uintptr_t)(TEGRA_PMC_BASE)
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static void enable_core_clocks(int cpu)
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{
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const uint32_t cpu0_clocks = CRC_RST_CPUG_CLR_CPU0 |
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CRC_RST_CPUG_CLR_DBG0 |
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CRC_RST_CPUG_CLR_CORE0 |
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CRC_RST_CPUG_CLR_CX0;
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const uint32_t cpu1_clocks = CRC_RST_CPUG_CLR_CPU1 |
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CRC_RST_CPUG_CLR_DBG1 |
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CRC_RST_CPUG_CLR_CORE1 |
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CRC_RST_CPUG_CLR_CX1;
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/* Clear reset of CPU components. */
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if (cpu == 0)
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write32(CLK_RST_REG(rst_cpug_cmplx_clr), cpu0_clocks);
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else
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write32(CLK_RST_REG(rst_cpug_cmplx_clr), cpu1_clocks);
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}
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static void set_armv8_32bit_reset_vector(uintptr_t entry)
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{
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void * const evp_cpu_reset_vector = EVP_CPU_RESET_VECTOR;
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write32(evp_cpu_reset_vector, entry);
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}
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static void set_armv8_64bit_reset_vector(uintptr_t entry)
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{
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struct tegra_pmc_regs * const pmc = PMC_REGS;
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/* Currently assume 32-bit addresses only. */
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write32(&pmc->secure_scratch34, entry);
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write32(&pmc->secure_scratch35, 0);
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}
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void cpu_prepare_startup(void *entry_64)
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{
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/* Warm reset vector is pulled from the PMC scratch registers. */
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set_armv8_64bit_reset_vector((uintptr_t)entry_64);
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/*
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* The Denver cores start in 32-bit mode. Therefore a trampoline
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* is needed to get into 64-bit mode. Point the cold reset vector
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* to the traompoline location.
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*/
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set_armv8_32bit_reset_vector((uintptr_t)reset_entry_32bit);
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}
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void start_cpu_silent(int cpu, void *entry_64)
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{
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cpu_prepare_startup(entry_64);
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enable_core_clocks(cpu);
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}
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void start_cpu(int cpu, void *entry_64)
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{
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printk(BIOS_DEBUG, "Starting CPU%d @ %p trampolining to %p.\n",
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cpu, reset_entry_32bit, entry_64);
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start_cpu_silent(cpu, entry_64);
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}
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