Karthikeyan Ramasubramanian 876cfe0ee2 spd/lp5: Generate initial SPDs for Sabrina SoC ... Mainboards using Sabrina SoC will be using LP5 memory technology. Generate the initial set of SPDs for the existing LP5 memory parts. BUG=b:211510456 TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>		2022-02-10 12:50:19 +00:00
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parts_spd_manifest.generated.txt	spd/lp5: Generate initial SPDs for Sabrina SoC	2022-02-10 12:50:19 +00:00
spd-1.hex	spd/lp5: Generate initial SPDs for Sabrina SoC	2022-02-10 12:50:19 +00:00
spd-2.hex	spd/lp5: Generate initial SPDs for Sabrina SoC	2022-02-10 12:50:19 +00:00
spd-3.hex	spd/lp5: Generate initial SPDs for Sabrina SoC	2022-02-10 12:50:19 +00:00
spd-empty.hex	spd/lp5: Generate initial SPDs for Sabrina SoC	2022-02-10 12:50:19 +00:00