0d6ddf8da7
The x86 timers are a bit of a mess. Cases where different stages use different counters and timestamps use different counters from udelays. The original intention was to only flip TSC_CONSTANT_RATE Kconfig to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those counters do run with a constant rate but we just lack tsc_freq_mhz() implementation for three platforms. Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a slow run of calibrate_tsc_with_pit(). This is easy enough to fix with followup implementation of tsc_freq_mhz() for the platforms. Implementations with LAPIC_MONOTONIC_TIMER typically will not have tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However, as they don't use TSC for udelay() the slow calibrate_tsc_with_pit() is avoided. Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900 claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch that romstage to use UDELAY_TSC. Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
187 lines
4.1 KiB
Text
187 lines
4.1 KiB
Text
# TODO These two options look too similar
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config PARALLEL_CPU_INIT
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bool
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default n
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config PARALLEL_MP
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def_bool n
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help
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This option uses common MP infrastructure for bringing up APs
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in parallel. It additionally provides a more flexible mechanism
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for sequencing the steps of bringing up the APs.
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config PARALLEL_MP_AP_WORK
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def_bool n
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depends on PARALLEL_MP
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help
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Allow APs to do other work after initialization instead of going
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to sleep.
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config UDELAY_LAPIC
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bool
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default n
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config LAPIC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_LAPIC
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help
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Expose monotonic time using the local APIC.
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config UDELAY_LAPIC_FIXED_FSB
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int
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config UDELAY_TSC
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bool
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default n
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config UNKNOWN_TSC_RATE
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bool
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default y if LAPIC_MONOTONIC_TIMER
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config TSC_MONOTONIC_TIMER
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def_bool n
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depends on UDELAY_TSC
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help
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Expose monotonic time using the TSC.
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config TSC_SYNC_LFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an lfence instruction in order to synchronize
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rdtsc. This is true for all modern AMD CPUs.
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config TSC_SYNC_MFENCE
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bool
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default n
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help
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The CPU driver should select this if the CPU needs
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to execute an mfence instruction in order to synchronize
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rdtsc. This is true for all modern Intel CPUs.
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config NO_FIXED_XIP_ROM_SIZE
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bool
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default n
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help
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The XIP_ROM_SIZE Kconfig variable is used globally on x86
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with the assumption that all chipsets utilize this value.
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For the chipsets which do not use the variable it can lead
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to unnecessary alignment constraints in cbfs for romstage.
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Therefore, allow those chipsets a path to not be burdened.
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config XIP_ROM_SIZE
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hex
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depends on !NO_FIXED_XIP_ROM_SIZE
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default 0x10000
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config SETUP_XIP_CACHE
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bool
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depends on C_ENVIRONMENT_BOOTBLOCK
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depends on !NO_XIP_EARLY_STAGES
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help
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Select this option to set up an MTRR to cache XIP stages loaded
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from the bootblock. This is useful on platforms lacking a
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non-eviction mode and therefore need to be careful to avoid
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eviction.
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config CPU_ADDR_BITS
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int
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default 36
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config LOGICAL_CPUS
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bool
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default y
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config HAVE_SMI_HANDLER
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bool
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default n
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depends on (SMM_ASEG || SMM_TSEG)
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config NO_SMM
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bool
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default n
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config SMM_ASEG
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bool
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default n
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depends on !NO_SMM
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config SMM_TSEG
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bool
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default y
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depends on !(NO_SMM || SMM_ASEG)
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if SMM_TSEG
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config SMM_MODULE_HEAP_SIZE
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hex
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default 0x4000
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help
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This option determines the size of the heap within the SMM handler
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modules.
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config SMM_MODULE_STACK_SIZE
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hex
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default 0x400
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help
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This option determines the size of the stack within the SMM handler
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modules.
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config SMM_STUB_STACK_SIZE
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hex
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default 0x400
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help
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This option determines the size of the stack within the SMM handler
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modules.
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endif
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config SMM_LAPIC_REMAP_MITIGATION
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bool
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default y if NORTHBRIDGE_INTEL_I945
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default y if NORTHBRIDGE_INTEL_GM45
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default y if NORTHBRIDGE_INTEL_NEHALEM
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default n
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config SERIALIZED_SMM_INITIALIZATION
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bool
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default n
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help
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On some CPUs, there is a race condition in SMM.
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This can occur when both hyperthreads change SMM state
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variables in parallel without coordination.
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Setting this option serializes the SMM initialization
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to avoid an ugly hang in the boot process at the cost
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of a slightly longer boot time.
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config X86_AMD_FIXED_MTRRS
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bool
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default n
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help
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This option informs the MTRR code to use the RdMem and WrMem fields
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in the fixed MTRR MSRs.
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config X86_AMD_INIT_SIPI
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bool
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default n
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help
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This option limits the number of SIPI signals sent during during the
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common AP setup. Intel documentation specifies an INIT SIPI SIPI
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sequence, however this doesn't work on some AMD platforms.
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config MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING
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def_bool n
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help
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On certain platforms a boot speed gain can be realized if mirroring
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the payload data stored in non-volatile storage. On x86 systems the
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payload would typically live in a memory-mapped SPI part. Copying
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the SPI contents to RAM before performing the load can speed up
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the boot process.
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config SOC_SETS_MSRS
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bool
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default n
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help
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The SoC requires different access methods for reading and writing
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the MSRs. Use SoC specific routines to handle the MSR access.
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