e9a0130879
Change-Id: I40f8b4c7cbc55e16929b1f40d18bb5a9c19845da Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29289 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
92 lines
2.7 KiB
C
92 lines
2.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015-2017 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <cpu/x86/msr.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <intelblocks/systemagent.h>
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/systemagent.h>
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#include "chip.h"
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bool soc_is_vtd_capable(void)
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{
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struct device *const root_dev = SA_DEV_ROOT;
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return root_dev &&
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!(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE);
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}
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/*
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* SoC implementation
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*
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* Add all known fixed memory ranges for Host Controller/Memory
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* controller.
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*/
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void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{
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static const struct sa_mmio_descriptor soc_fixed_resources[] = {
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{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
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"PCIEXBAR" },
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{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
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{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
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{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
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{ GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" },
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{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
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};
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const struct soc_intel_skylake_config *const config = dev->chip_info;
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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ARRAY_SIZE(soc_fixed_resources));
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if (!(config && config->ignore_vtd) && soc_is_vtd_capable())
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sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
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ARRAY_SIZE(soc_vtd_resources));
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}
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/*
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* SoC implementation
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*
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* Perform System Agent Initialization during Ramstage phase.
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*/
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void soc_systemagent_init(struct device *dev)
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{
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/* Enable Power Aware Interrupt Routing */
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enable_power_aware_intr();
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/* Enable BIOS Reset CPL */
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enable_bios_reset_cpl();
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/* Configure turbo power limits 1ms after reset complete bit */
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mdelay(1);
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set_power_limits(28);
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}
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int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base,
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uint64_t *prmrr_mask)
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{
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msr_t msr;
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msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_BASE);
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*prmrr_base = (uint64_t) msr.hi << 32 | msr.lo;
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msr = rdmsr(MSR_UNCORE_PRMRR_PHYS_MASK);
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*prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo;
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return 0;
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}
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