95be012c11
The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in the SPI flash. New flashmap region is created for that purpose. The goal of caching is to reduce the dependency on CSME and the HECI IP LOAD command which may fail when the CSME is disabled, e.g. soft disabled by HECI command or HAP disabled. This change allows to keep PCIe 5.0 root ports functioning even if CSME/HECI is not functional. TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port is functional after loading the HSPHY from cache. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f Reviewed-on: https://review.coreboot.org/c/coreboot/+/68987 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
21 lines
574 B
Text
21 lines
574 B
Text
# layout for firmware residing at top of 4GB address space
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# +-------------+ <-- 4GB - ROM_SIZE / start of flash
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# | unspecified |
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# +-------------+ <-- 4GB - BIOS_SIZE
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# | FMAP |
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# +-------------+ <-- 4GB - BIOS_SIZE + FMAP_SIZE
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# | CBFS |
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# +-------------+ <-- 4GB / end of flash
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FLASH@##ROM_BASE## ##ROM_SIZE## {
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BIOS@##BIOS_BASE## ##BIOS_SIZE## {
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##CONSOLE_ENTRY##
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##MRC_CACHE_ENTRY##
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##SMMSTORE_ENTRY##
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##SPD_CACHE_ENTRY##
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##VPD_ENTRY##
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##HSPHY_FW_ENTRY##
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FMAP@##FMAP_BASE## ##FMAP_SIZE##
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COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
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}
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}
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