1a73eb08e7
On an ASRock H81M-HDS neither libgfxinit, nor Linux, is able to
initialise the display when lanes are not configured to be shared
between DDI A and DDI E.
Intel's reference manual [1] states that the decision to share lanes
between DDI A and DDI E is "based on board configuration". Hence, add a
new field to the devicetree that boards can set. All existing Haswell
boards have this unset, thus taking a value of 0, so there is no change
to existing behaviour.
[1]: Intel Open Source Graphics Programmer's Reference Manual (PRM)
Volume 2c: Command Reference: Registers (Haswell)
https://01.org/linuxgraphics/documentation/hardware-specification-prms/2013-intel-core-processor-family
Change-Id: I6f7832293215d2b53e31b0a5c985e6098eb72f1b
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29385
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
50 lines
1.7 KiB
C
50 lines
1.7 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef NORTHBRIDGE_INTEL_HASWELL_CHIP_H
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#define NORTHBRIDGE_INTEL_HASWELL_CHIP_H
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#include <drivers/intel/gma/i915.h>
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/*
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* Digital Port Hotplug Enable:
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* 0x04 = Enabled, 2ms short pulse
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* 0x05 = Enabled, 4.5ms short pulse
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* 0x06 = Enabled, 6ms short pulse
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* 0x07 = Enabled, 100ms short pulse
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*/
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struct northbridge_intel_haswell_config {
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u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
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u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
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u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
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u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
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u8 gpu_panel_power_cycle_delay; /* T4 time sequence */
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u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */
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u16 gpu_panel_power_down_delay; /* T3 time sequence */
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u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */
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u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
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u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
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u32 gpu_pch_backlight; /* PCH Backlight PWM value */
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bool gpu_ddi_e_connected;
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struct i915_gpu_controller_info gfx;
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};
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extern struct chip_operations northbridge_intel_haswell_ops;
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#endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */
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