240 lines
7.0 KiB
HTML
240 lines
7.0 KiB
HTML
<!DOCTYPE html>
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<html>
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<head>
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<title>Board</title>
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</head>
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<body>
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<h1>x86 Board Development</h1>
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<p>
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Board development requires System-on-a-Chip (SoC) support.
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The combined steps are listed
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<a target="_blank" href="../development.html">here</a>.
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The development steps for the board are listed below:
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</p>
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<ol>
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<li><a href="#RequiredFiles">Required Files</a></li>
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<li>Enable <a href="#SerialOutput">Serial Output</a></li>
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<li>Load the <a href="#SpdData">Memory Timing Data</a></li>
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<li><a href="#DisablePciDevices">Disable</a> the PCI devices</li>
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<li><a href="#AcpiTables">ACPI Tables</a></li>
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</ol>
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<hr>
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<h2><a name="RequiredFiles">Required Files</a></h2>
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<p>
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Create the board directory as src/mainboard/<Vendor>/<Board>.
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</p>
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<p>
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The following files are required to build a new board:
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</p>
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<ol>
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<li>Kconfig.name - Defines the Kconfig value for the board</li>
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<li>Kconfig
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<ol type="A">
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<li>Selects the SoC for the board and specifies the SPI flash size
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<ol type="I">
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<li>BOARD_ROMSIZE_KB_<Size></li>
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<li>SOC_<Vendor>_<Chip Family></li>
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</ol>
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</li>
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<li>Declare the Kconfig values for:
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<ol type="I">
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<li>MAINBOARD_DIR</li>
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<li>MAINBOARD_PART_NUMBER</li>
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<li>MAINBOARD_VENDOR</li>
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</ol>
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</li>
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</ol>
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</li>
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<li>devicetree.cb - Enable root bridge and serial port
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<ol type="A">
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<li>The first line must be "chip soc/Intel/<soc family>";
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this path is used by the generated static.c to include the chip.h
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header file
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</li>
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</ol>
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</li>
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<li>romstage.c
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<ol type="A">
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<li>Add routine mainboard_romstage_entry which calls romstage_common</li>
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</ol>
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</li>
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<li>Configure coreboot build:
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<ol type="A">
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<li>Set LOCALVERSION</li>
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<li>Select vendor for the board</li>
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<li>Select the board</li>
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<li>CBFS_SIZE = 0x00100000</li>
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<li>Set the CPU_MICROCODE_CBFS_LEN</li>
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<li>Set the CPU_MICROCODE_CBFS_LOC</li>
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<li>Set the FSP_IMAGE_ID_STRING</li>
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<li>Set the FSP_LOC</li>
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<li>No payload</li>
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<li>Choose the default value for all other options</li>
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</ol>
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</li>
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</ol>
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<hr>
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<h2><a name="SerialOutput">Enable Serial Output</a></h2>
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<p>
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Use the following steps to enable serial output:
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</p>
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<ol>
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<li>Implement the car_mainboard_pre_console_init routine in the com_init.c
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file:
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<ol type="A">
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<li>Power on and enable the UART controller</li>
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<li>Connect the UART receive and transmit data lines to the
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appropriate SoC pins
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</li>
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</ol>
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</li>
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<li>Add Makefile.inc
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<ol type="A">
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<li>Add com_init.c to romstage</li>
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</ol>
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</li>
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</ol>
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<hr>
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<h2><a name="SpdData">Memory Timing Data</a></h2>
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<p>
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Memory timing data is located in the flash. This data is in the format of
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<a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a>
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(SPD) data.
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Use the following steps to load the SPD data:
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</p>
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<ol>
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<li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the
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display of the SPD data being passed to MemoryInit
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</li>
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<li>Create an "spd" subdirectory</li>
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<li>Create an spd/spd.c file for the SPD implementation
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<ol type="A">
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<li>Implement the mainboard_fill_spd_data routine
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<ol type="i">
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<li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li>
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<li>Fill in the pei_data structure with SPD data for each of the DIMMs</li>
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<li>Set the DIMM channel configuration</li>
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</ol>
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</li>
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</ol>
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</li>
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<li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li>
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<li>Create spd/Makefile.inc
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<ol type="A">
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<li>Add spd.c to romstage</li>
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<li>Add the .spd.hex file to SPD_SOURCES</li>
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</ol>
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</li>
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<li>Edit Makefile.inc to add the spd subdirectory</li>
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<li>Edit romstage.c
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<ol type="A">
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<li>Call mainboard_fill_spd_data</li>
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<li>Add mainboard_memory_init_params to copy the SPD and DRAM
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configuration data from the pei_data structure into the UPDs
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for MemoryInit
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</li>
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</ol>
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</li>
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<li>Edit devicetree.cb
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<ol type="A">
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<li>Include the UPD parameters for MemoryInit except for:
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<ul>
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<li>Address of SPD data</li>
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<li>DRAM configuration set above</li>
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</ul>
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</li>
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</ol>
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</li>
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<li>A working FSP
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<a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a>
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routine is required to complete debugging</li>
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<li>Debug the result until port 0x80 outputs
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<ol type="A">
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<li>0x34:
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- Just after entering
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l67">raminit</a>
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</li>
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<li>0x36:
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- Just before displaying the
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l106">UPD parameters</a>
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for FSP MemoryInit
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</li>
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<li>0x92: <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l219">POST_FSP_MEMORY_INIT</a>
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- Just before calling FSP
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l125">MemoryInit</a>
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</li>
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<li>0x37:
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- Just after returning from FSP
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<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/raminit.c;hb=HEAD#l127">MemoryInit</a>
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</li>
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</ol>
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</li>
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<li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li>
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</ol>
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<hr>
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<h2><a name="DisablePciDevices">Disable PCI Devices</a></h2>
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<p>
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Ramstage's BS_DEV_ENUMERATE state displays the PCI vendor and device IDs for all
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of the devices in the system. Edit the devicetree.cb file:
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</p>
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<ol>
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<li>Edit the devicetree.cb file:
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<ol type="A">
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<li>Add an entry for a PCI device.function and turn it off. The entry
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should look similar to:
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<pre><code>device pci 14.0 off end</code></pre>
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</li>
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<li>Turn on the devices for:
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<ul>
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<li>Memory Controller</li>
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<li>Debug serial device</li>
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</ul>
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</li>
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</ol>
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</li>
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<li>Debug until the BS_DEV_ENUMERATE state shows the proper state for all of the devices</li>
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</ol>
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<hr>
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<h2><a name="AcpiTables">ACPI Tables</a></h2>
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<ol>
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<li>Edit Kconfig
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<ol type="A">
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<li>Add "select HAVE_ACPI_TABLES"</li>
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</ol>
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</li>
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<li>Add the acpi_tables.c module:
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<ol type="A">
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<li>Include soc/acpi.h</li>
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<li>Add the acpi_create_fadt routine
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<ol type="I">
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<li>fill in the ACPI header</li>
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<li>Call the acpi_fill_in_fadt routine</li>
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</ol>
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</li>
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</ol>
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</li>
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<li>Add the dsdt.asl module:
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</li>
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</ol>
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<hr>
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<p>Modified: 20 February 2016</p>
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</body>
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</html>
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