29cc9eda20
Major changes: 1. Separate resource allocation into: A. Read Resources B. Avoid fixed resources (constrain limits) C. Allocate resources D. Set resources Usage notes: Resources which have IORESOURCE_FIXED set in the flags constrain the placement of other resources. All fixed resources will end up outside (above or below) the allocated resources. Domains usually start with base = 0 and limit = 2^address_bits - 1. I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is still there for resources. Some platforms may want to change that, but I didn't want to break anyone's board. Resources are allocated in a single block for memory and another for I/O. Currently the resource allocator doesn't support holes. Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
101 lines
2.9 KiB
C
101 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <pc80/isa-dma.h>
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#include <pc80/mc146818rtc.h>
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#include "i82371eb.h"
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static void isa_init(struct device *dev)
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{
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u16 reg16;
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u32 reg32;
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/* Initialize the real time clock (RTC). */
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rtc_init(0);
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/* Enable access to all BIOS regions. */
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reg16 = pci_read_config16(dev, XBCS);
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reg16 |= LOWER_BIOS_ENABLE;
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reg16 |= EXT_BIOS_ENABLE;
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reg16 |= EXT_BIOS_ENABLE_1MB;
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reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */
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pci_write_config16(dev, XBCS, reg16);
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/*
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* The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
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* bus, which is a subset of ISA. We select the full ISA bus here.
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*/
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reg32 = pci_read_config32(dev, GENCFG);
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reg32 |= ISA; /* Select ISA, not EIO. */
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pci_write_config16(dev, GENCFG, reg32);
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/* Initialize ISA DMA. */
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isa_dma_init();
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}
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static void sb_read_resources(struct device *dev)
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{
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struct resource *res;
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pci_dev_read_resources(dev);
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res = new_resource(dev, 1);
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res->base = 0x0UL;
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res->size = 0x1000UL;
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res->limit = 0xffffUL;
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res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, 2);
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res->base = 0xff800000UL;
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res->size = 0x00800000UL; /* 8 MB for flash */
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, 3); /* IOAPIC */
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res->base = 0xfec00000;
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res->size = 0x00001000;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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}
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const struct device_operations isa_ops = {
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.read_resources = sb_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = isa_init,
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.scan_bus = scan_static_bus, /* TODO: Needed? */
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.enable = 0,
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.ops_pci = 0, /* No subsystem IDs on 82371EB! */
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};
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static const struct pci_driver isa_driver __pci_driver = {
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.ops = &isa_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82371AB_ISA,
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};
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static const struct pci_driver isa_SB_driver __pci_driver = {
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.ops = &isa_ops,
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.vendor = PCI_VENDOR_ID_INTEL,
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.device = PCI_DEVICE_ID_INTEL_82371SB_ISA,
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};
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