d509ee55b6
Drop LPC pad configuration code since all boards now do pad configuration on their own. The comment about LPC_CLKRUNB when using eSPI is moved to `Documentation/getting_started/gpio.md`. Change-Id: I710d6aee8c3b2c8282cd321cd0688b9b26abea07 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49410 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
20 lines
420 B
C
20 lines
420 B
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#include <device/pci.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/rtc.h>
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#include <soc/pcr_ids.h>
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#include <soc/pm.h>
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#include "chip.h"
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void lpc_soc_init(struct device *dev)
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{
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const struct soc_intel_apollolake_config *cfg;
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cfg = config_of(dev);
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/* Set LPC Serial IRQ mode */
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lpc_set_serirq_mode(cfg->serirq_mode);
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/* Initialize RTC */
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rtc_init();
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}
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