York Yang e1e11e63af intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP ... Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration by UPD input. Update UPD_DATA_REGION structure for matching up this FSP change. PcdCustomerRevision is a debugging aid that will be output to debug message in FSP. When needed, it can be customized by BCT tool for tracking BCT configurations. Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b Signed-off-by: York Yang <york.yang@intel.com> Reviewed-on: http://review.coreboot.org/8107 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless@gmail.com>		2015-01-31 23:09:26 +01:00
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amd	vendorcode/amd/agesa/f14: update microcode	2015-01-31 07:23:35 +01:00
google	vboot2: copy tlcl from vboot_reference as a preparation for vboot2 integration	2015-01-27 01:43:57 +01:00
intel	intel/rangeley: Update UPD_DATA_REGION to support POST-GOLD 2 FSP	2015-01-31 23:09:26 +01:00
Kconfig	AMD Steppe Eagle: Add binary PI vendorcode files	2014-08-30 19:13:45 +02:00
Makefile.inc	Add Intel FSP northbridge support Sandybridge and Ivybridge	2013-12-04 18:45:13 +01:00