894e3a9ec8
This UART is used in the SiFive FU540 SoC, and will probably be used in other SoCs in the future. Change-Id: I915edf39666b7a5f9550e3b7e743e97fe3cacfd3 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/25768 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
114 lines
2.9 KiB
C
114 lines
2.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Jonathan Neuschäfer
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <boot/coreboot_tables.h>
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#include <console/uart.h>
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#include <types.h>
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/*
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* This is a driver for SiFive's own UART, documented in the FU540 manual:
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* https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/
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*/
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struct sifive_uart_registers {
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uint32_t txdata; /* Transmit data register */
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uint32_t rxdata; /* Receive data register */
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uint32_t txctrl; /* Transmit control register */
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uint32_t rxctrl; /* Receive control register */
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uint32_t ie; /* UART interrupt enable */
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uint32_t ip; /* UART interrupt pending */
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uint32_t div; /* Baud rate divisor */
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} __packed;
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#define TXDATA_FULL BIT(31)
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#define RXDATA_EMPTY BIT(31)
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#define TXCTRL_TXEN BIT(0)
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#define TXCTRL_NSTOP_SHIFT 1
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#define TXCTRL_NSTOP(x) (((x)-1) << TXCTRL_NSTOP_SHIFT)
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#define TXCTRL_TXCNT_SHIFT 16
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#define TXCTRL_TXCNT(x) ((x) << TXCTRL_TXCNT_SHIFT)
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#define RXCTRL_RXEN BIT(0)
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#define RXCTRL_RXCNT_SHIFT 16
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#define RXCTRL_RXCNT(x) ((x) << RXCTRL_RXCNT_SHIFT)
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#define IP_TXWM BIT(0)
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#define IP_RXWM BIT(1)
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void uart_init(int idx)
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{
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struct sifive_uart_registers *regs = uart_platform_baseptr(idx);
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/* TODO: Configure the divisor */
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/* Enable transmission, one stop bit, transmit watermark at 1 */
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write32(®s->txctrl, TXCTRL_TXEN|TXCTRL_NSTOP(1)|TXCTRL_TXCNT(1));
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/* Enable reception, receive watermark at 0 */
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write32(®s->rxctrl, RXCTRL_RXEN|RXCTRL_RXCNT(0));
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}
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static bool uart_can_tx(struct sifive_uart_registers *regs)
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{
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return !(read32(®s->txdata) & TXDATA_FULL);
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}
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void uart_tx_byte(int idx, unsigned char data)
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{
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struct sifive_uart_registers *regs = uart_platform_baseptr(idx);
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while (!uart_can_tx(regs))
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; /* TODO: implement a timeout */
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write32(®s->txdata, data);
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}
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void uart_tx_flush(int idx)
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{
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struct sifive_uart_registers *regs = uart_platform_baseptr(idx);
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uint32_t ip;
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/* Use the TX watermark bit to find out if the TX FIFO is empty */
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do {
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ip = read32(®s->ip);
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} while (!(ip & IP_TXWM));
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}
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unsigned char uart_rx_byte(int idx)
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{
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struct sifive_uart_registers *regs = uart_platform_baseptr(idx);
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uint32_t rxdata;
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do {
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rxdata = read32(®s->rxdata);
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} while (rxdata & RXDATA_EMPTY);
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return rxdata & 0xff;
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}
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unsigned int uart_input_clock_divider(void)
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{
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/*
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* The SiFive UART handles oversampling internally. The divided clock
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* is the baud clock.
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*/
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return 1;
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}
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#ifndef __PRE_RAM__
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void uart_fill_lb(void *data)
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{
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/* TODO */
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}
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#endif
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