3a4e201a21
Update bitWidthPerChannel in memory_parts.json and re-generate the SPD. Then the device boots successfully with DDR H9JCNNNFA5MLYR-N6E. BUG=b:261530632 BRANCH=None TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5 Change-Id: Ib78c2e28394206b59c41b6b28cf24d8a756f7ae9 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> |
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| .. | ||
| set-0 | ||
| set-1 | ||
| memory_parts.json | ||
| platforms_manifest.generated.txt | ||