Aaron Durbin 24079323d4 soc/amd/stoneyridge: provide alternate monotonic timer ... The TSC has been observed to be ticking at a non-constant rate in early boot. The root cause is still not known, but this misbehavior necessitates an alternative monotonic timer source. Use the perf TSC which ticks at 100 MHz. This also means the timestamp table is not accurate as well. Root cause of TSC rate instability needs to be resolved in order to fix that. BUG=b:72170796 Change-Id: Ie052169868a9d9f25f8cc0ce8dd8251b560e671f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/23397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>		2018-01-24 16:27:03 +00:00
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amd	soc/amd/stoneyridge: provide alternate monotonic timer	2018-01-24 16:27:03 +00:00
broadcom	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
dmp	DMP Vortex86ex board & chip: Remove - using LATE_CBMEM_INIT	2018-01-15 23:23:17 +00:00
imgtec	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
intel	soc/intel/cannonlake: Add child CARD device into eMMC/SD controller	2018-01-24 13:28:31 +00:00
lowrisc	RISC-V boards: Stop using the config string	2017-11-07 12:31:00 +00:00
marvell	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
mediatek	soc/mediatek/mt8173: Remove cast of NULL* to void *	2017-11-03 16:03:30 +00:00
nvidia	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
qualcomm	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
rockchip	soc/rockchip/rk3399: Ensure full eDP init sequence	2018-01-10 20:57:17 +00:00
samsung	soc: Add Kconfig for each soc vendor	2017-10-23 17:18:32 +00:00
ucb	riscv: Remove config string support	2017-12-02 05:25:00 +00:00