360 lines
11 KiB
C
360 lines
11 KiB
C
#include "linux_syscall.h"
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#include "linux_console.h"
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int log2(int value)
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{
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/* __builtin_bsr is a exactly equivalent to the x86 machine
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* instruction with the exception that it returns -1
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* when the value presented to it is zero.
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* Otherwise __builtin_bsr returns the zero based index of
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* the highest bit set.
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*/
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return __builtin_bsr(value);
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}
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static int smbus_read_byte(unsigned device, unsigned address)
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{
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static const unsigned char dimm[] = {
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0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01,
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0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40,
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0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0x80, 0x08, 0x07, 0x0d, 0x0a, 0x02, 0x48, 0x00, 0x04, 0x60, 0x70, 0x02, 0x82, 0x08, 0x08, 0x01,
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0x0e, 0x04, 0x0c, 0x01, 0x02, 0x20, 0x00, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48, 0x2a, 0x40,
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0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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};
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return dimm[(device << 8) + address];
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}
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#define SMBUS_MEM_DEVICE_START 0x00
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#define SMBUS_MEM_DEVICE_END 0x01
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#define SMBUS_MEM_DEVICE_INC 1
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/* Function 2 */
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#define DRAM_CONFIG_HIGH 0x94
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#define DCH_MEMCLK_SHIFT 20
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#define DCH_MEMCLK_MASK 7
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#define DCH_MEMCLK_100MHZ 0
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#define DCH_MEMCLK_133MHZ 2
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#define DCH_MEMCLK_166MHZ 5
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#define DCH_MEMCLK_200MHZ 7
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/* Function 3 */
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#define NORTHBRIDGE_CAP 0xE8
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#define NBCAP_128Bit 0x0001
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#define NBCAP_MP 0x0002
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#define NBCAP_BIG_MP 0x0004
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#define NBCAP_ECC 0x0004
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#define NBCAP_CHIPKILL_ECC 0x0010
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#define NBCAP_MEMCLK_SHIFT 5
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#define NBCAP_MEMCLK_MASK 3
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#define NBCAP_MEMCLK_100MHZ 3
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#define NBCAP_MEMCLK_133MHZ 2
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#define NBCAP_MEMCLK_166MHZ 1
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#define NBCAP_MEMCLK_200MHZ 0
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#define NBCAP_MEMCTRL 0x0100
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typedef unsigned char uint8_t;
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typedef unsigned int uint32_t;
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static unsigned spd_to_dimm(unsigned device)
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{
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return (device - SMBUS_MEM_DEVICE_START);
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}
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static void disable_dimm(unsigned index)
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{
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print_debug("disabling dimm");
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print_debug_hex8(index);
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print_debug("\r\n");
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#if 0
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pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+0)<<2), 0);
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pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CSBASE + (((index << 1)+1)<<2), 0);
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#endif
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}
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struct mem_param {
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uint8_t cycle_time;
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uint32_t dch_memclk;
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};
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static const struct mem_param *get_mem_param(unsigned min_cycle_time)
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{
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static const struct mem_param speed[] = {
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{
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.cycle_time = 0xa0,
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.dch_memclk = DCH_MEMCLK_100MHZ << DCH_MEMCLK_SHIFT,
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},
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{
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.cycle_time = 0x75,
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.dch_memclk = DCH_MEMCLK_133MHZ << DCH_MEMCLK_SHIFT,
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},
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{
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.cycle_time = 0x60,
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.dch_memclk = DCH_MEMCLK_166MHZ << DCH_MEMCLK_SHIFT,
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},
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{
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.cycle_time = 0x50,
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.dch_memclk = DCH_MEMCLK_200MHZ << DCH_MEMCLK_SHIFT,
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},
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{
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.cycle_time = 0x00,
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},
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};
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const struct mem_param *param;
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for(param = &speed[0]; param->cycle_time ; param++) {
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if (min_cycle_time > (param+1)->cycle_time) {
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break;
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}
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}
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if (!param->cycle_time) {
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die("min_cycle_time to low");
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}
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return param;
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}
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#if 1
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static void debug(int c)
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{
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print_debug_char(c);
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print_debug_char('\r');
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print_debug_char('\n');
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}
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#endif
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static const struct mem_param *spd_set_memclk(void)
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{
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/* Compute the minimum cycle time for these dimms */
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const struct mem_param *param;
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unsigned min_cycle_time, min_latency;
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unsigned device;
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uint32_t value;
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static const int latency_indicies[] = { 26, 23, 9 };
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static const unsigned char min_cycle_times[] = {
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[NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */
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[NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */
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[NBCAP_MEMCLK_133MHZ] = 0x75, /* 7.5ns */
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[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
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};
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#if 0
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value = pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP);
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#else
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value = 0x50;
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#endif
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min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
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min_latency = 2;
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#if 1
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print_debug("min_cycle_time: ");
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print_debug_hex8(min_cycle_time);
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print_debug(" min_latency: ");
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print_debug_hex8(min_latency);
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print_debug("\r\n");
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#endif
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/* Compute the least latency with the fastest clock supported
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* by both the memory controller and the dimms.
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*/
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for(device = SMBUS_MEM_DEVICE_START;
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device <= SMBUS_MEM_DEVICE_END;
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device += SMBUS_MEM_DEVICE_INC)
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{
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int new_cycle_time, new_latency;
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int index;
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int latencies;
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int latency;
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debug('A');
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/* First find the supported CAS latencies
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* Byte 18 for DDR SDRAM is interpreted:
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* bit 0 == CAS Latency = 1.0
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* bit 1 == CAS Latency = 1.5
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* bit 2 == CAS Latency = 2.0
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* bit 3 == CAS Latency = 2.5
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* bit 4 == CAS Latency = 3.0
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* bit 5 == CAS Latency = 3.5
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* bit 6 == TBD
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* bit 7 == TBD
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*/
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new_cycle_time = 0xa0;
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new_latency = 5;
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latencies = smbus_read_byte(device, 18);
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if (latencies <= 0) continue;
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debug('B');
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/* Compute the lowest cas latency supported */
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latency = log2(latencies) -2;
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/* Loop through and find a fast clock with a low latency */
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for(index = 0; index < 3; index++, latency++) {
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int value;
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debug('C');
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if ((latency < 2) || (latency > 4) ||
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(!(latencies & (1 << latency)))) {
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continue;
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}
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debug('D');
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value = smbus_read_byte(device, latency_indicies[index]);
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if (value < 0) continue;
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debug('E');
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/* Only increase the latency if we decreas the clock */
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if ((value >= min_cycle_time) && (value < new_cycle_time)) {
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new_cycle_time = value;
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new_latency = latency;
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#if 1
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print_debug("device: ");
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print_debug_hex8(device);
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print_debug(" new_cycle_time: ");
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print_debug_hex8(new_cycle_time);
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print_debug(" new_latency: ");
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print_debug_hex8(new_latency);
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print_debug("\r\n");
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#endif
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}
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debug('G');
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}
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debug('H');
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#if 1
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print_debug("device: ");
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print_debug_hex8(device);
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print_debug(" new_cycle_time: ");
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print_debug_hex8(new_cycle_time);
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print_debug(" new_latency: ");
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print_debug_hex8(new_latency);
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print_debug("\r\n");
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#endif
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if (new_latency > 4){
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continue;
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}
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debug('I');
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/* Does min_latency need to be increased? */
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if (new_cycle_time > min_cycle_time) {
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min_cycle_time = new_cycle_time;
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}
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/* Does min_cycle_time need to be increased? */
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if (new_latency > min_latency) {
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min_latency = new_latency;
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}
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#if 1
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print_debug("device: ");
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print_debug_hex8(device);
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print_debug(" min_cycle_time: ");
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print_debug_hex8(min_cycle_time);
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print_debug(" min_latency: ");
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print_debug_hex8(min_latency);
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print_debug("\r\n");
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#endif
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}
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/* Make a second pass through the dimms and disable
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* any that cannot support the selected memclk and cas latency.
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*/
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for(device = SMBUS_MEM_DEVICE_START;
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device <= SMBUS_MEM_DEVICE_END;
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device += SMBUS_MEM_DEVICE_INC)
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{
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int latencies;
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int latency;
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int index;
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int value;
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int dimm;
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latencies = smbus_read_byte(device, 18);
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if (latencies <= 0) {
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goto dimm_err;
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}
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/* Compute the lowest cas latency supported */
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latency = log2(latencies) -2;
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/* Walk through searching for the selected latency */
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for(index = 0; index < 3; index++, latency++) {
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if (!(latencies & (1 << latency))) {
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continue;
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}
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if (latency == min_latency)
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break;
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}
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/* If I can't find the latency or my index is bad error */
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if ((latency != min_latency) || (index >= 3)) {
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goto dimm_err;
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}
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/* Read the min_cycle_time for this latency */
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value = smbus_read_byte(device, latency_indicies[index]);
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/* All is good if the selected clock speed
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* is what I need or slower.
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*/
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if (value <= min_cycle_time) {
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continue;
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}
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/* Otherwise I have an error, disable the dimm */
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dimm_err:
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disable_dimm(spd_to_dimm(device));
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}
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#if 1
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print_debug("min_cycle_time: ");
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print_debug_hex8(min_cycle_time);
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print_debug(" min_latency: ");
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print_debug_hex8(min_latency);
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print_debug("\r\n");
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#endif
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/* Now that I know the minimum cycle time lookup the memory parameters */
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param = get_mem_param(min_cycle_time);
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#if 0
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/* Update DRAM Config High with our selected memory speed */
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value = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_HIGH);
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value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
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value |= param->dch_memclk;
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pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_HIGH, value);
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static const unsigned latencies[] = { 1, 5, 2 };
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/* Update DRAM Timing Low wiht our selected cas latency */
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value = pci_read_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW);
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value &= ~7;
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value |= latencies[min_latency - 2];
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pci_write_config32(PCI_DEV(0, 0x18, 2), DRAM_CONFIG_LOW, value);
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#endif
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return param;
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}
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static void main(void)
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{
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const struct mem_param *param;
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param = spd_set_memclk();
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_exit(0);
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}
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