a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
108 lines
2.9 KiB
Text
108 lines
2.9 KiB
Text
##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2009 coresystems GmbH
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## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
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##
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## This program is free software; you can redistribute it and/or
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## modify it under the terms of the GNU General Public License as
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## published by the Free Software Foundation; version 2 of
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## the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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chip northbridge/intel/i945
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# IGD Displays
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register "gfx.ndid" = "3"
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register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
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register "gpu_hotplug" = "0x00000220"
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register "gpu_lvds_use_spread_spectrum_clock" = "1"
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register "gpu_backlight" = "0x1290128"
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device cpu_cluster 0 on
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chip cpu/intel/socket_mFCPGA478
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device lapic 0 on end
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end
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end
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device domain 0 on
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device pci 00.0 on # Host bridge
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subsystemid 0x8086 0x7270
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end
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device pci 02.0 on # VGA controller
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subsystemid 0x8086 0x7270
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end
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device pci 02.1 on # display controller
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subsystemid 0x17aa 0x201a
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end
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chip southbridge/intel/i82801gx
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register "pirqa_routing" = "0x0b"
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register "pirqb_routing" = "0x0b"
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register "pirqc_routing" = "0x0b"
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register "pirqd_routing" = "0x0b"
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register "pirqe_routing" = "0x0b"
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register "pirqf_routing" = "0x0b"
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register "pirqg_routing" = "0x0b"
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register "pirqh_routing" = "0x0b"
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# GPI routing
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# 0 No effect (default)
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# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
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# 2 SCI (if corresponding GPIO_EN bit is also set)
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register "gpi1_routing" = "2"
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register "gpi7_routing" = "2"
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register "sata_ahci" = "0x1"
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register "sata_ports_implemented" = "0x04"
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register "gpe0_en" = "0x11000006"
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register "alt_gp_smi_en" = "0x1000"
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register "ide_enable_primary" = "1"
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register "ide_enable_secondary" = "1"
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register "c4onc3_enable" = "1"
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register "c3_latency" = "0x23"
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register "p_cnt_throttling_supported" = "1"
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device pci 1b.0 on # Audio Controller
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subsystemid 0x8384 0x7680
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end
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device pci 1c.0 on end # Ethernet
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device pci 1c.1 on end # Atheros WLAN
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device pci 1d.0 on # USB UHCI
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subsystemid 0x8086 0x7270
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end
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device pci 1d.1 on # USB UHCI
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subsystemid 0x8086 0x7270
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end
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device pci 1d.2 on # USB UHCI
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subsystemid 0x8086 0x7270
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end
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device pci 1d.3 on # USB UHCI
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subsystemid 0x8086 0x7270
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end
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device pci 1d.7 on # USB2 EHCI
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subsystemid 0x8086 0x7270
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end
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device pci 1f.0 on # PCI-LPC bridge
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subsystemid 0x8086 0x7270
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end
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device pci 1f.1 on # IDE
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subsystemid 0x8086 0x7270
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end
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device pci 1f.2 on # SATA
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subsystemid 0x8086 0x7270
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end
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device pci 1f.3 on # SMBUS
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subsystemid 0x8086 0x7270
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end
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end
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end
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end
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