a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
80 lines
2.2 KiB
C
80 lines
2.2 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <southbridge/amd/cimx/cimx_util.h>
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#include "SBPLATFORM.h"
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//#define SMBUS_IO_BASE 0x6000
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void set_pcie_reset(void);
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void set_pcie_dereset(void);
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/**
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* TODO
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* SB CIMx callback
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*/
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void set_pcie_reset(void)
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{
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}
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/**
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* TODO
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* mainboard specific SB CIMx callback
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*/
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void set_pcie_dereset(void)
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{
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}
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/**********************************************
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* Enable the dedicated functions of the board.
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**********************************************/
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static void mainboard_enable(device_t dev)
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{
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printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
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/* Power off unused clock pins of GPP PCIe devices */
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u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
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/*
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* GPP CLK0 connected to unpopulated mini PCIe slot
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* GPP CLK1 connected to ethernet chip
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*/
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write8(misc_mem_clk_cntrl + 0, 0xFF);
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/* GPP CLK2 connected to the external USB3 controller */
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write8(misc_mem_clk_cntrl + 1, 0x0F);
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write8(misc_mem_clk_cntrl + 2, 0x00);
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write8(misc_mem_clk_cntrl + 3, 0x00);
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/* SLT_GFX_CLK connected to PCIe slot */
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write8(misc_mem_clk_cntrl + 4, 0xF0);
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/*
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* Initialize ASF registers to an arbitrary address because someone
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* long ago set things up this way inside the SPD read code. The
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* SPD read code has been made generic and moved out of the board
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* directory, so the ASF init is being done here.
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*/
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pm_iowrite(0x29, 0x80);
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pm_iowrite(0x28, 0x61);
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}
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struct chip_operations mainboard_ops = {
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.enable_dev = mainboard_enable,
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};
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