0e9dbf0843
Even though the register name begins with ESPI, it resides in the SPI registers and not in the eSPI registers, so add a comment to point this out to hopefully avoid some confusion. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9f8d15ceb98f51aad0816021f98ec5c78953e7f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
19 lines
435 B
C
19 lines
435 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <amdblocks/spi.h>
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#include <soc/espi.h>
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#include <types.h>
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#define ESPI_CNTRL_REGISTER 0x10 /* SPI register, not eSPI register! */
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#define LOCK_SPIX10_BIT2 BIT(3)
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#define ESPI_MUX_SPI1 BIT(2)
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#define ROM_ADDR_WR_PROT BIT(1)
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void espi_switch_to_spi1_pads(void)
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{
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uint8_t reg = spi_read8(ESPI_CNTRL_REGISTER);
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reg |= ESPI_MUX_SPI1;
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spi_write8(ESPI_CNTRL_REGISTER, reg);
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}
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