8c190f3518
While we cannot recreate exact copies of PC Engines APU1 firmware images, I shall upstream the vital changes for coreboot from the following tarballs SAGE has published to meet GPL: SageBios_PCEngines_APU_sources_for_publishing_20140405_GPL_package.tar.gz md5sum: ce5f54723e4fe3b63a1a3e35586728d4 pcengines.apu_139_osp.tar.gz md5sum: af6c8ab3b85d1a5a9fbeb41efa30a1ef The patch here adds Kconfig, Makefile.inc and devicetree.cb files to match 2014/04/05 release tarball config.h and static.c files. Change-Id: Id61270b4d484f712a5c0e780a01fc81f1550b9ad Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8325 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
70 lines
2.1 KiB
Text
70 lines
2.1 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 Advanced Micro Devices, Inc.
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* DefinitionBlock Statement */
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DefinitionBlock (
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"DSDT.AML", /* Output filename */
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"DSDT", /* Signature */
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0x02, /* DSDT Revision, needs to be 2 for 64bit */
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"PCENG ", /* OEMID */
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"COREBOOT", /* TABLE ID */
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0x00010001 /* OEM Revision */
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)
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{ /* Start of ASL file */
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/* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */
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#include "acpi/mainboard.asl"
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#include <cpu/amd/agesa/family14/acpi/cpu.asl>
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#include "acpi/routing.asl"
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Scope(\_SB) {
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/* global utility methods expected within the \_SB scope */
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#include <arch/x86/acpi/globutil.asl>
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Device(PCI0) {
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/* Describe the AMD Northbridge */
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#include <northbridge/amd/agesa/family14/acpi/northbridge.asl>
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/* Describe the AMD Fusion Controller Hub Southbridge */
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#include <southbridge/amd/cimx/sb800/acpi/fch.asl>
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/* Primary (and only) IDE channel */
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Device(IDEC) {
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Name(_ADR, 0x00140001)
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#include "acpi/ide.asl"
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} /* end IDEC */
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}
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} /* End Scope(_SB) */
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/* Contains the supported sleep states for this chipset */
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#include <southbridge/amd/cimx/sb800/acpi/sleepstates.asl>
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/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
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#include "acpi/sleep.asl"
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#include "acpi/gpe.asl"
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#include <southbridge/amd/cimx/sb800/acpi/smbus.asl>
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#include "acpi/thermal.asl"
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}
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/* End of ASL file */
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