bd4af105c4
`fsp/util.h` draws incompatible UDK headers in. Hence, we have to declare it locally again. Change-Id: Iaa5981088eeb5c36f765d6332ae47a38a6a4c875 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40729 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
158 lines
4.6 KiB
Makefile
158 lines
4.6 KiB
Makefile
ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_BASE),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/intel/microcode
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subdirs-y += ../../../cpu/intel/turbo
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subdirs-y += ../../../cpu/x86/lapic
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subdirs-y += ../../../cpu/x86/mtrr
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subdirs-y += ../../../cpu/x86/smm
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subdirs-y += ../../../cpu/x86/tsc
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subdirs-y += ../../../cpu/intel/common
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bootblock-y += bootblock/bootblock.c
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bootblock-y += bootblock/cpu.c
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bootblock-y += bootblock/pch.c
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bootblock-y += pmutil.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += gspi.c
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bootblock-y += i2c.c
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bootblock-y += spi.c
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bootblock-y += lpc.c
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bootblock-y += p2sb.c
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bootblock-y += uart.c
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romstage-y += cnl_memcfg_init.c
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romstage-y += gspi.c
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romstage-y += i2c.c
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romstage-y += lpc.c
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romstage-y += pmutil.c
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romstage-y += reset.c
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romstage-y += spi.c
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romstage-y += uart.c
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ramstage-y += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += elog.c
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ramstage-y += finalize.c
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ramstage-y += fsp_params.c
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ramstage-y += gspi.c
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ramstage-y += i2c.c
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ramstage-y += lockdown.c
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ramstage-y += lpc.c
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ramstage-y += me.c
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ramstage-y += nhlt.c
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ramstage-y += p2sb.c
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ramstage-y += pmc.c
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ramstage-y += pmutil.c
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ramstage-y += reset.c
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ramstage-y += smmrelocate.c
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ramstage-y += spi.c
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ramstage-y += systemagent.c
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ramstage-y += uart.c
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ramstage-y += vr_config.c
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ramstage-y += sd.c
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ramstage-y += xhci.c
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smm-y += elog.c
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smm-y += p2sb.c
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smm-y += pmc.c
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smm-y += pmutil.c
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smm-y += smihandler.c
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smm-y += uart.c
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smm-y += xhci.c
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postcar-y += pmutil.c
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postcar-y += i2c.c
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postcar-y += gspi.c
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postcar-y += spi.c
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postcar-y += uart.c
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verstage-y += gspi.c
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verstage-y += i2c.c
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verstage-y += pmutil.c
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verstage-y += spi.c
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verstage-y += uart.c
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ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y)
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bootblock-y += gpio_cnp_h.c
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romstage-y += gpio_cnp_h.c
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ramstage-y += gpio_cnp_h.c
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smm-y += gpio_cnp_h.c
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verstage-y += gpio_cnp_h.c
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else
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bootblock-y += gpio.c
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romstage-y += gpio.c
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ramstage-y += gpio.c
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smm-y += gpio.c
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verstage-y += gpio.c
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endif
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bootblock-y += gpio_common.c
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ramstage-y += gpio_common.c
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ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y)
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# Not yet in intel-microcode repo
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#cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-66-*)
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else ifeq ($(CONFIG_SOC_INTEL_COFFEELAKE),y)
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ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y)
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0a
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0b
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0c
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-0d
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else
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a
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endif
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else ifeq ($(CONFIG_SOC_INTEL_WHISKEYLAKE),y)
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0b
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0c
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else ifeq ($(CONFIG_SOC_INTEL_COMETLAKE),y)
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ifneq ($(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H),y)
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# Missing 06-a6-01
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0c
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cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-a6-00
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endif
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endif
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake
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CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include
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# DSP firmware settings files.
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NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/cnl/nhlt-blobs
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DMIC_1CH_48KHZ_16B = dmic-1ch-48khz-16b.bin
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DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin
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DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin
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MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin
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DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin
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MAX98373_RENDER_24B = max98373-render-2ch-48khz-24b.bin
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MAX98373_RENDER_16B = max98373-render-2ch-48khz-16b.bin
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cbfs-files-$(CONFIG_NHLT_DMIC_1CH_16B) += $(DMIC_1CH_48KHZ_16B)
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$(DMIC_1CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_1CH_48KHZ_16B)
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$(DMIC_1CH_48KHZ_16B)-type := raw
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cbfs-files-$(CONFIG_NHLT_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B)
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$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B)
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$(DMIC_2CH_48KHZ_16B)-type := raw
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cbfs-files-$(CONFIG_NHLT_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B)
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$(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B)
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$(DMIC_4CH_48KHZ_16B)-type := raw
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cbfs-files-$(CONFIG_NHLT_MAX98357) += $(MAX98357_RENDER)
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$(MAX98357_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98357_RENDER)
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$(MAX98357_RENDER)-type := raw
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cbfs-files-$(CONFIG_NHLT_MAX98373) += $(MAX98373_RENDER_16B)
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$(MAX98373_RENDER_16B)-file := $(NHLT_BLOB_PATH)/$(MAX98373_RENDER_16B)
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$(MAX98373_RENDER_16B)-type := raw
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cbfs-files-$(CONFIG_NHLT_MAX98373) += $(MAX98373_RENDER_24B)
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$(MAX98373_RENDER_24B)-file := $(NHLT_BLOB_PATH)/$(MAX98373_RENDER_24B)
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$(MAX98373_RENDER_24B)-type := raw
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cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE)
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$(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE)
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$(DA7219_RENDER_CAPTURE)-type := raw
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endif
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