coreboot-kgpe-d16/src/soc/intel
Wenkai Du 038cce2c2e broadwell: Fix incorrect SATA port map mask
WPT-LP has 4 SATA ports. Current code assumes 6 SATA ports and as a result,
some reserved bits are written with 1. No specific issue has been observed
so far.

BUG=None
BRANCH=None
TEST=Verify SATA PCI configure space dump on Auron

Change-Id: I737719b3d5cd788158cd5b6991405ba098be4078
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 2b55587a74ac5d45354dc123937b562290468855
Original-Change-Id: I9c53ac86e2bf72901647bd2cfa48ac0ce31abea0
Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/233661
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9479
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-04-13 13:00:56 +02:00
..
baytrail baytrail: correct NC pin to GPO pin according to BYT platform design guide 2015-04-10 20:33:04 +02:00
broadwell broadwell: Fix incorrect SATA port map mask 2015-04-13 13:00:56 +02:00
common baytrail: Fix hdmi audio choppy issue 2015-04-06 19:06:37 +02:00
fsp_baytrail build system: rename __BOOT_BLOCK__ and __VER_STAGE__ 2015-04-04 20:07:18 +02:00
Makefile.inc broadwell: Hook into the build system 2014-12-31 21:23:09 +01:00