f1b58b7835
PCI config accessors are no longer indirectly included from <arch/io.h> use <device/pci_ops.h> instead. Change-Id: I2adf46430a33bc52ef69d1bf7dca4655fc8475bd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
175 lines
3.9 KiB
C
175 lines
3.9 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <cpu/x86/smm.h>
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#include <southbridge/intel/i82801gx/nvs.h>
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#include <southbridge/intel/common/pmutil.h>
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#include <ec/acpi/ec.h>
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#include "dock.h"
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#include "smi.h"
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#define GPE_EC_SCI 12
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#define LVTMA_BL_MOD_LEVEL 0x7af9 /* ATI Radeon backlight level */
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static void mainboard_smm_init(void)
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{
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printk(BIOS_DEBUG, "initializing SMI\n");
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/* Enable 0x1600/0x1600 register pair */
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ec_set_bit(0x00, 0x05);
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}
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static void mainboard_smi_brightness_down(void)
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{
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u8 *bar;
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if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
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printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL));
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*(bar+LVTMA_BL_MOD_LEVEL) &= 0xf0;
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if (*(bar+LVTMA_BL_MOD_LEVEL) > 0x10)
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*(bar+LVTMA_BL_MOD_LEVEL) -= 0x10;
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}
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}
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static void mainboard_smi_brightness_up(void)
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{
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u8 *bar;
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if ((bar = (u8 *)pci_read_config32(PCI_DEV(1, 0, 0), 0x18))) {
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printk(BIOS_DEBUG, "bar: %08X, level %02X\n", (unsigned int)bar, *(bar+LVTMA_BL_MOD_LEVEL));
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*(bar+LVTMA_BL_MOD_LEVEL) |= 0x0f;
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if (*(bar+LVTMA_BL_MOD_LEVEL) < 0xf0)
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*(bar+LVTMA_BL_MOD_LEVEL) += 0x10;
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}
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}
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int mainboard_io_trap_handler(int smif)
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{
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static int smm_initialized;
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if (!smm_initialized) {
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mainboard_smm_init();
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smm_initialized = 1;
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}
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switch (smif) {
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case SMI_DOCK_CONNECT:
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/* If there's an legacy I/O module present, we're not
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* allowed to connect the Docking LPC Bus, as both Super I/O
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* chips are using 0x2e as base address.
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*/
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if (legacy_io_present())
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break;
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if (!dock_connect()) {
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/* set dock LED to indicate status */
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ec_write(0x0c, 0x08);
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ec_write(0x0c, 0x89);
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} else {
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/* blink dock LED to indicate failure */
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ec_write(0x0c, 0xc8);
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ec_write(0x0c, 0x09);
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}
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break;
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case SMI_DOCK_DISCONNECT:
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dock_disconnect();
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ec_write(0x0c, 0x09);
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ec_write(0x0c, 0x08);
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break;
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case SMI_BRIGHTNESS_UP:
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mainboard_smi_brightness_up();
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break;
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case SMI_BRIGHTNESS_DOWN:
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mainboard_smi_brightness_down();
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break;
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default:
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return 0;
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}
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/* On success, the IO Trap Handler returns 1
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* On failure, the IO Trap Handler returns a value != 1 */
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return 1;
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}
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static void mainboard_smi_handle_ec_sci(void)
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{
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u8 status = inb(EC_SC);
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u8 event;
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if (!(status & EC_SCI_EVT))
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return;
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event = ec_query();
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printk(BIOS_DEBUG, "EC event %02x\n", event);
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switch (event) {
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/* brightness up */
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case 0x14:
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mainboard_smi_brightness_up();
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break;
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/* brightness down */
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case 0x15:
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mainboard_smi_brightness_down();
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break;
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/* Fn-F9 Key */
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case 0x18:
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/* power loss */
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case 0x27:
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/* undock event */
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case 0x50:
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mainboard_io_trap_handler(SMI_DOCK_DISCONNECT);
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break;
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/* dock event */
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case 0x37:
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mainboard_io_trap_handler(SMI_DOCK_CONNECT);
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break;
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default:
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break;
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}
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}
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void mainboard_smi_gpi(u32 gpi)
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{
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if (gpi & (1 << GPE_EC_SCI))
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mainboard_smi_handle_ec_sci();
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}
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int mainboard_smi_apmc(u8 data)
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{
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switch (data) {
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case APM_CNT_ACPI_ENABLE:
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/* use 0x1600/0x1604 to prevent races with userspace */
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ec_set_ports(0x1604, 0x1600);
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/* route H8SCI to SCI */
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gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI);
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break;
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case APM_CNT_ACPI_DISABLE:
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/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
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provide a EC query function */
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ec_set_ports(0x66, 0x62);
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/* route H8SCI# to SMI */
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gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI);
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break;
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default:
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break;
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}
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return 0;
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}
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