coreboot-kgpe-d16/src/mainboard/siemens/mc_ehl
Werner Zeh 8dd1a54f09 mb/siemens/mc_ehl1: Adjust PCIe settings in devicetree
This board does not use CLKREQ-signaling for PCIe, so disable the pin
assignments. In addition only three clock outputs are used for PCIe,
therefore disable all others to improve EMI.

Change-Id: I545f890fa55a109df7f44d2c82170874fb769009
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56455
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-22 09:40:57 +00:00
..
variants mb/siemens/mc_ehl1: Adjust PCIe settings in devicetree 2021-07-22 09:40:57 +00:00
board_info.txt
bootblock.c
dsdt.asl
Kconfig mb/siemens/mc_ehl: Switch to 16 MB ROM and provide a flashmap 2021-07-07 14:56:54 +00:00
Kconfig.name
mainboard.c
Makefile.inc
mc_ehl.fmd mb/siemens/mc_ehl: Switch to 16 MB ROM and provide a flashmap 2021-07-07 14:56:54 +00:00
romstage_fsp_params.c