277 lines
8.0 KiB
C
277 lines
8.0 KiB
C
/* This file is part of the superiotool project */
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef SUPERIOTOOL_H
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#define SUPERIOTOOL_H
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <string.h>
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#include <getopt.h>
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#if defined(__GLIBC__)
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#include <sys/io.h>
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#endif
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#if (defined(__MACH__) && defined(__APPLE__))
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/* DirectHW is available here: https://www.coreboot.org/DirectHW */
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#include <DirectHW/DirectHW.h>
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#endif
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#ifdef PCI_SUPPORT
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# ifdef __NetBSD__
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#include <pciutils/pci.h>
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# else
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#include <pci/pci.h>
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# endif
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#endif
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#if defined(__FreeBSD__)
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#include <sys/types.h>
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#include <machine/cpufunc.h>
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#define OUTB(x, y) do { u_int tmp = (y); outb(tmp, (x)); } while (0)
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#define OUTW(x, y) do { u_int tmp = (y); outw(tmp, (x)); } while (0)
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#define OUTL(x, y) do { u_int tmp = (y); outl(tmp, (x)); } while (0)
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#define INB(x) __extension__ ({ u_int tmp = (x); inb(tmp); })
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#define INW(x) __extension__ ({ u_int tmp = (x); inw(tmp); })
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#define INL(x) __extension__ ({ u_int tmp = (x); inl(tmp); })
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#else
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#define OUTB outb
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#define OUTW outw
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#define OUTL outl
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#define INB inb
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#define INW inw
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#define INL inl
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#endif
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#if defined(__NetBSD__) && (defined(__i386__) || defined(__x86_64__))
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#include <sys/types.h>
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#include <machine/sysarch.h>
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#if defined(__i386__)
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#define iopl i386_iopl
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#elif defined(__x86_64__)
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#define iopl x86_64_iopl
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#endif
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static __inline__ void
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outb(uint8_t value, uint16_t port)
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{
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__asm__ __volatile__ ("outb %b0,%w1": :"a" (value), "Nd" (port));
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}
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static __inline__ void
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outw(uint16_t value, uint16_t port)
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{
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__asm__ __volatile__ ("outw %w0,%w1": :"a" (value), "Nd" (port));
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}
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static __inline__ void
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outl(uint32_t value, uint16_t port)
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{
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__asm__ __volatile__ ("outl %0,%w1": :"a" (value), "Nd" (port));
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}
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static __inline__ uint8_t inb(uint16_t port)
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{
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uint8_t value;
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__asm__ __volatile__ ("inb %w1,%0":"=a" (value):"Nd" (port));
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return value;
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}
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static __inline__ uint16_t inw(uint16_t port)
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{
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uint16_t value;
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__asm__ __volatile__ ("inw %w1,%0":"=a" (value):"Nd" (port));
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return value;
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}
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static __inline__ uint32_t inl(uint16_t port)
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{
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uint32_t value;
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__asm__ __volatile__ ("inl %1,%0":"=a" (value):"Nd" (port));
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return value;
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}
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#endif
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#define USAGE "Usage: superiotool [-d] [-e] [-a] [-l] [-V] [-v] [-h]\n\n\
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-d | --dump Dump Super I/O register contents\n\
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-e | --extra-dump Dump secondary registers too (e.g. EC registers)\n\
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-a | --alternate-dump Use alternative dump format, more suitable for diff\n\
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-l | --list-supported Show the list of supported Super I/O chips\n\
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-V | --verbose Verbose mode\n\
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-v | --version Show the superiotool version\n\
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-h | --help Show a short help text\n\n"
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#define USAGE_INFO "\
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Per default (no options) superiotool will just probe for a Super I/O\n\
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and print its vendor, name, ID, revision, and config port.\n"
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#define NOTFOUND " Failed. Returned data: "
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#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
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#define EOT -1 /* End Of Table */
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#define NOLDN -2 /* NO LDN needed */
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#define NANA -3 /* Not Available:
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Used for registers having externally controlled
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values that can change during runtime like
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GPIO input value registers. */
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#define RSVD -4 /* Reserved */
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#define MISC -5 /* Needs special comment in output:
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Used for registers depending on external pin straps
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configuring static, but board-specific settings like
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SIO base address or AMD/Intel power seqencing type. */
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#define MAXLDN 0x14 /* Biggest LDN */
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#define LDNSIZE (MAXLDN + 3) /* Biggest LDN + 0 + NOLDN + EOT */
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#define MAXNUMIDX 170 /* Maximum number of indices */
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#define IDXSIZE (MAXNUMIDX + 1)
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#define MAXNUMPORTS (6 + 1) /* Maximum number of Super I/O ports */
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/* Select registers for various components. */
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#define LDN_SEL 0x07 /* LDN select register */
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#define WINBOND_HWM_SEL 0x4e /* Hardware monitor bank select */
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/* Command line parameters. */
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extern int dump, verbose, extra_dump;
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extern int chip_found;
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struct superio_registers {
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int32_t superio_id; /* Signed, as we need EOT. */
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const char *name; /* Super I/O name */
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struct {
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int8_t ldn;
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const char *name; /* LDN name */
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int16_t idx[IDXSIZE];
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int16_t def[IDXSIZE];
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} ldn[LDNSIZE];
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};
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/* pci.c */
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#ifdef PCI_SUPPORT
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extern struct pci_access *pacc;
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struct pci_dev *pci_dev_find(uint16_t vendor, uint16_t device);
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#endif
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/* superiotool.c */
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uint8_t regval(uint16_t port, uint8_t reg);
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void regwrite(uint16_t port, uint8_t reg, uint8_t val);
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void enter_conf_mode_winbond_fintek_ite_8787(uint16_t port);
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void exit_conf_mode_winbond_fintek_ite_8787(uint16_t port);
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void enter_conf_mode_fintek_7777(uint16_t port);
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void exit_conf_mode_fintek_7777(uint16_t port);
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int superio_unknown(const struct superio_registers reg_table[], uint16_t id);
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const char *get_superio_name(const struct superio_registers reg_table[],
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uint16_t id);
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void dump_superio(const char *name, const struct superio_registers reg_table[],
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uint16_t port, uint16_t id, uint8_t ldn_sel);
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void dump_io(uint16_t iobase, uint16_t length);
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void dump_data(uint16_t iobase, int bank);
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void probing_for(const char *vendor, const char *info, uint16_t port);
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void print_vendor_chips(const char *vendor,
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const struct superio_registers reg_table[]);
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/* ali.c */
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void probe_idregs_ali(uint16_t port);
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void print_ali_chips(void);
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/* aspeed.c */
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void probe_idregs_aspeed(uint16_t port);
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void print_aspeed_chips(void);
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/* amd.c */
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void probe_idregs_amd(uint16_t port);
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void print_amd_chips(void);
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/* serverengines.c */
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void probe_idregs_serverengines(uint16_t port);
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void print_serverengines_chips(void);
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/* exar.c */
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void probe_idregs_exar(uint16_t port);
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void print_exar_chips(void);
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/* fintek.c */
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void probe_idregs_fintek(uint16_t port);
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void probe_idregs_fintek_alternative(uint16_t port);
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void print_fintek_chips(void);
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/* infineon.c */
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void probe_idregs_infineon(uint16_t port);
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void print_infineon_chips(void);
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/* ite.c */
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void probe_idregs_ite(uint16_t port);
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void print_ite_chips(void);
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/* nsc.c */
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void probe_idregs_nsc(uint16_t port);
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void print_nsc_chips(void);
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/* nuvoton.c */
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void probe_idregs_nuvoton(uint16_t port);
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void print_nuvoton_chips(void);
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/* smsc.c */
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void probe_idregs_smsc(uint16_t port);
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void print_smsc_chips(void);
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/* winbond.c */
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void probe_idregs_winbond(uint16_t port);
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void print_winbond_chips(void);
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/* via.c */
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#ifdef PCI_SUPPORT
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void probe_idregs_via(uint16_t port);
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void print_via_chips(void);
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#endif
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/** Table of which config ports to probe for each Super I/O family. */
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static const struct {
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void (*probe_idregs) (uint16_t port);
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int ports[MAXNUMPORTS]; /* Signed, as we need EOT. */
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} superio_ports_table[] = {
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{probe_idregs_ali, {0x3f0, 0x370, EOT}},
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{probe_idregs_aspeed, {0x2e, 0x4e, EOT}},
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{probe_idregs_exar, {0x2e, 0x4e, EOT}},
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{probe_idregs_fintek, {0x2e, 0x4e, EOT}},
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{probe_idregs_fintek_alternative, {0x2e, 0x4e, EOT}},
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/* Only use 0x370 for ITE, but 0x3f0 or 0x3bd would also be valid. */
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{probe_idregs_ite, {0x20e, 0x25e, 0x2e, 0x4e, 0x370, 0x6e, EOT}},
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{probe_idregs_nsc, {0x2e, 0x4e, 0x15c, 0x164e, EOT}},
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/* I/O pairs on Nuvoton EC chips can be configured by firmware in
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* addition to the following hardware strapping options. */
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{probe_idregs_nuvoton, {0x164e, 0x2e, 0x4e, EOT}},
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{probe_idregs_smsc, {0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370, EOT}},
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{probe_idregs_winbond, {0x2e, 0x4e, 0x3f0, 0x370, 0x250, EOT}},
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#ifdef PCI_SUPPORT
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{probe_idregs_via, {0x2e, 0x4e, 0x3f0, EOT}},
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/* in fact read the BASE from HW */
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{probe_idregs_amd, {0xaa, EOT}},
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#endif
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{probe_idregs_serverengines, {0x2e, EOT}},
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{probe_idregs_infineon, {0x2e, 0x4e, EOT}},
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};
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/** Table of functions to print out supported Super I/O chips. */
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static const struct {
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void (*print_list) (void);
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} vendor_print_functions[] = {
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{print_ali_chips},
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{print_exar_chips},
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{print_fintek_chips},
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{print_ite_chips},
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{print_nsc_chips},
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{print_nuvoton_chips},
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{print_smsc_chips},
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{print_winbond_chips},
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#ifdef PCI_SUPPORT
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{print_via_chips},
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{print_amd_chips},
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{print_aspeed_chips},
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#endif
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{print_serverengines_chips},
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{print_infineon_chips},
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};
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#endif
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