6de8b42482
List of changes:
1. Create Module Type macros as per Memory Type
(i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation
issue due to renaming of existing macros due to scoping the Memory
Type.
2. Use dedicated Memory Type and Module type for `Form Factor`
and `TypeDetail` conversion using `get_spd_info()` function.
3. Create a new API (convert_form_factor_to_module_type()) for
`Form Factor` to 'Module type' conversion as per `Memory Type`.
4. Add new argument as `Memory Type` to
smbios_form_factor_to_spd_mod_type() so that it can internally
call convert_form_factor_to_module_type() for `Module Type`
conversion.
5. Update `test_smbios_form_factor_to_spd_mod_type()` to
accommodate different memory types.
6. Skip fixed module type to form factor conversion using DDR2 SPD4
specification (inside dimm_info_fill()).
Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx.
BUG=b:194659789
TEST=Refer to dmidecode -t 17 output as below:
Without this code change:
Handle 0x0012, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 16 bits
Size: 2048 MB
Form Factor: Unknown
....
With this code change:
Handle 0x0012, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 16 bits
Size: 2048 MB
Form Factor: Row Of Chips
....
Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
80 lines
1.9 KiB
C
80 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/dram/spd.h>
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#include <dimm_info_util.h>
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#include <smbios.h>
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#include <spd.h>
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#include <console/console.h>
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uint8_t smbios_bus_width_to_spd_width(uint8_t ddr_type, uint16_t total_width,
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uint16_t data_width)
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{
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uint8_t out;
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/* Lookup table as defined in the JEDEC Standard. */
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switch (data_width) {
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case 64:
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out = MEMORY_BUS_WIDTH_64;
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break;
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case 32:
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out = MEMORY_BUS_WIDTH_32;
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break;
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case 16:
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out = MEMORY_BUS_WIDTH_16;
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break;
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case 8:
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out = MEMORY_BUS_WIDTH_8;
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break;
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default:
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printk(BIOS_NOTICE, "Unknown memory size %hu", data_width);
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/*
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* The SMBIOS spec says we should set 0xFFFF on an unknown
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* value, but we don't have a way of passing that signal via SPD
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* encoded values.
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*/
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out = MEMORY_BUS_WIDTH_8;
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break;
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}
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uint16_t extension_bits = total_width - data_width;
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switch (extension_bits) {
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case 8:
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if (ddr_type == MEMORY_TYPE_DDR5 || ddr_type == MEMORY_TYPE_LPDDR5)
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out |= SPD_ECC_8BIT_LP5_DDR5;
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else
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out |= SPD_ECC_8BIT;
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break;
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case 0:
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/* No extension bits */
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break;
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default:
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printk(BIOS_NOTICE, "Unknown number of extension bits %hu",
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extension_bits);
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break;
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}
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return out;
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}
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uint32_t smbios_memory_size_to_mib(uint16_t memory_size, uint32_t extended_size)
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{
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/* Memory size is unknown */
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if (memory_size == 0xFFFF)
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return 0;
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/* (32 GiB - 1 MiB) or greater is expressed in the extended size. */
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else if (memory_size == 0x7FFF)
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return extended_size;
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/* When the MSB is flipped, the value is specified in kilobytes */
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else if (memory_size & 0x8000)
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return (memory_size ^ 0x8000) / KiB;
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/* Value contains MiB */
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else
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return memory_size;
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}
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uint8_t smbios_form_factor_to_spd_mod_type(smbios_memory_type memory_type,
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smbios_memory_form_factor form_factor)
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{
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return convert_form_factor_to_module_type(memory_type, form_factor);
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}
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