c545baaf47
Always clear vector 0 entry before optionally overwriting it with the i8259 timer redirection. Change-Id: Ia2e96f43e6494711f9fc4fd74229f5817b04b48d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55286 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
152 lines
3.7 KiB
C
152 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <assert.h>
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#include <device/mmio.h>
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#include <arch/ioapic.h>
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#include <console/console.h>
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#include <cpu/x86/lapic.h>
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u32 io_apic_read(void *ioapic_base, u32 reg)
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{
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write32(ioapic_base, reg);
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return read32(ioapic_base + 0x10);
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}
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void io_apic_write(void *ioapic_base, u32 reg, u32 value)
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{
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write32(ioapic_base, reg);
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write32(ioapic_base + 0x10, value);
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}
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static void write_vector(void *ioapic_base, u8 vector, u32 high, u32 low)
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{
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io_apic_write(ioapic_base, vector * 2 + 0x10, low);
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io_apic_write(ioapic_base, vector * 2 + 0x11, high);
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printk(BIOS_SPEW, "IOAPIC: vector 0x%02x value 0x%08x 0x%08x\n",
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vector, high, low);
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}
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static int ioapic_interrupt_count(void *ioapic_base)
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{
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/* Read the available number of interrupts. */
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int ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
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if (!ioapic_interrupts || ioapic_interrupts == 0xff)
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ioapic_interrupts = 23;
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ioapic_interrupts += 1; /* Bits 23-16 specify the maximum redirection
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entry, which is the number of interrupts
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minus 1. */
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printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
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return ioapic_interrupts;
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}
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static void clear_vectors(void *ioapic_base, u8 first, u8 last)
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{
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u32 low, high;
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u8 i;
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printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at %p\n", ioapic_base);
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low = INT_DISABLED;
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high = NONE;
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for (i = first; i <= last; i++)
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write_vector(ioapic_base, i, high, low);
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if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
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printk(BIOS_WARNING, "IOAPIC not responding.\n");
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return;
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}
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}
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void clear_ioapic(void *ioapic_base)
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{
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clear_vectors(ioapic_base, 0, ioapic_interrupt_count(ioapic_base) - 1);
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}
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static void route_i8259_irq0(void *ioapic_base)
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{
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u32 bsp_lapicid = lapicid();
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u32 low, high;
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ASSERT(bsp_lapicid < 255);
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printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
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bsp_lapicid);
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/* Enable Virtual Wire Mode. Should this be LOGICAL_DEST instead? */
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low = INT_ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
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high = bsp_lapicid << (56 - 32);
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write_vector(ioapic_base, 0, high, low);
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if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
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printk(BIOS_WARNING, "IOAPIC not responding.\n");
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return;
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}
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}
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void set_ioapic_id(void *ioapic_base, u8 ioapic_id)
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{
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int i;
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printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at %p\n",
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ioapic_base);
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if (ioapic_id) {
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printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
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/* Set IOAPIC ID if it has been specified. */
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io_apic_write(ioapic_base, 0x00,
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(io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) |
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(ioapic_id << 24));
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}
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printk(BIOS_SPEW, "IOAPIC: Dumping registers\n");
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for (i = 0; i < 3; i++)
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printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i,
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io_apic_read(ioapic_base, i));
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}
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u8 get_ioapic_id(void *ioapic_base)
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{
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return (io_apic_read(ioapic_base, 0x00) >> 24) & 0x0f;
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}
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u8 get_ioapic_version(void *ioapic_base)
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{
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return io_apic_read(ioapic_base, 0x01) & 0xff;
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}
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void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb)
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{
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if (irq_on_fsb) {
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/*
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* For the Pentium 4 and above APICs deliver their interrupts
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* on the front side bus, enable that.
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*/
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printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
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io_apic_write(ioapic_base, 0x03,
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io_apic_read(ioapic_base, 0x03) | (1 << 0));
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} else {
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printk(BIOS_DEBUG,
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"IOAPIC: Enabling interrupts on APIC serial bus\n");
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io_apic_write(ioapic_base, 0x03, 0);
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}
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}
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void setup_ioapic_helper(void *ioapic_base, u8 ioapic_id, bool enable_virtual_wire)
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{
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set_ioapic_id(ioapic_base, ioapic_id);
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clear_ioapic(ioapic_base);
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if (enable_virtual_wire)
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route_i8259_irq0(ioapic_base);
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}
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void setup_ioapic(void *ioapic_base, u8 ioapic_id)
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{
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setup_ioapic_helper(ioapic_base, ioapic_id, true);
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}
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