1eaaa0e446
As the southbridge largely controls the PCI[e] configuration space this patch moves the resource allocation from the northbridge to the southbridge when the extended configuration space region is enabled. Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/12050 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
291 lines
9.6 KiB
C
291 lines
9.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/ioapic.h>
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#include <lib.h>
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#include "sr5650.h"
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#include "cmn.h"
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/* Table 6-6 Recommended Interrupt Routing Configuration */
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typedef struct _apic_device_info {
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u8 group;
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u8 swizzle;
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u8 pin;
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} apic_device_info;
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#define ABCD 0
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#define BCDA 1
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#define CDAB 2
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#define DABC 3
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static const apic_device_info default_apic_device_info_t [] = {
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/* Group Swizzling Port Int Pin */
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[0] = {0, 0, 31}, /* HT */
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[1] = {0, 0, 31}, /* IOMMU */
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[2] = {0, ABCD, 28}, /* Dev2 Grp0 [Int - 0..3] */
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[3] = {1, ABCD, 28}, /* Dev3 Grp1 [Int - 4..7] */
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[4] = {5, ABCD, 28}, /* Dev4 Grp5 [Int - 20..23] */
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[5] = {5, CDAB, 28}, /* Dev5 Grp5 [Int - 20..23] */
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[6] = {6, BCDA, 29}, /* Dev6 Grp6 [Int - 24..27] */
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[7] = {6, CDAB, 29}, /* Dev7 Grp6 [Int - 24..27] */
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[8] = {0, 0, 0 }, /* Reserved */
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[9] = {6, ABCD, 29}, /* Dev9 Grp6 [Int - 24..27] */
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[10] = {5, BCDA, 30}, /* Dev10 Grp5 [Int - 20..23] */
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[11] = {2, ABCD, 30}, /* Dev11 Grp2 [Int - 8..11] */
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[12] = {3, ABCD, 30}, /* Dev12 Grp3 [Int - 12..15] */
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[13] = {4, ABCD, 30} /* Dev13 Grp4 [Int - 16..19] */
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};
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/* These define names are common, so undefine them to avoid potential issues in other code */
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#undef ABCD
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#undef BCDA
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#undef CDAB
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#undef DABC
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/* Init APIC of sr5690 */
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static void sr5690_apic_init(struct device *dev)
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{
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u32 dword;
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const apic_device_info *entry = default_apic_device_info_t;
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/* rpr6.2.(2). Write to the IOAPIC Features Enable register */
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pci_write_config32(dev, 0xF8, 0x0);
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pci_write_config32(dev, 0xFC, 0x1F);
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/* rpr6.2.(3). Write to the remaining interrupt routing registers */
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/* IOAPICCMISCIND:0x3, group & swizzle of Dev 2,3,4,5 */
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dword = (entry[2].group | entry[2].swizzle << 4) << 0 |
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(entry[3].group | entry[3].swizzle << 4) << 8 |
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(entry[4].group | entry[4].swizzle << 4) << 16 |
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(entry[5].group | entry[5].swizzle << 4) << 24;
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pci_write_config32(dev, 0xF8, 0x3);
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pci_write_config32(dev, 0xFC, dword);
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/* IOAPICCMISCIND:0x4, group & swizzle of Dev 6,7,9,10 */
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dword = (entry[6].group | entry[6].swizzle << 4) << 0 |
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(entry[7].group | entry[7].swizzle << 4) << 8 |
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(entry[9].group | entry[9].swizzle << 4) << 16 |
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(entry[10].group | entry[10].swizzle << 4) << 24;
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pci_write_config32(dev, 0xF8, 0x4);
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pci_write_config32(dev, 0xFC, dword);
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/* IOAPICCMISCIND:0x5, group & swizzle of Dev 11,12,13 */
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dword = (entry[11].group | entry[11].swizzle << 4) << 0 |
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(entry[12].group | entry[12].swizzle << 4) << 8 |
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(entry[13].group | entry[13].swizzle << 4) << 16;
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pci_write_config32(dev, 0xF8, 0x5);
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pci_write_config32(dev, 0xFC, dword);
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/* IOAPICCMISCIND:0x6, pin map of dev 2,3,4,5 */
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dword = entry[2].pin |
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entry[3].pin << 8 |
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entry[4].pin << 16|
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entry[5].pin << 24;
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pci_write_config32(dev, 0xF8, 0x6);
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pci_write_config32(dev, 0xFC, dword);
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/* IOAPICCMISCIND:0x7, pin map of dev 6,7,8,9 */
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dword = entry[6].pin |
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entry[7].pin << 8 |
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entry[8].pin << 16|
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entry[9].pin << 24;
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pci_write_config32(dev, 0xF8, 0x7);
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pci_write_config32(dev, 0xFC, dword);
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/* IOAPICCMISCIND:0x8, pin map of dev 10,11,12,13 */
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dword = entry[10].pin |
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entry[11].pin << 8 |
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entry[12].pin << 16|
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entry[13].pin << 24;
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pci_write_config32(dev, 0xF8, 0x8);
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pci_write_config32(dev, 0xFC, dword);
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/* IOAPICCMISCIND:0x9, pin map of ht, iommu */
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dword = entry[0].pin | entry[1].pin << 8;
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pci_write_config32(dev, 0xF8, 0x9);
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pci_write_config32(dev, 0xFC, dword);
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pci_write_config32(dev, 0xF8, 0x1);
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dword = pci_read_config32(dev, 0xFC) & 0xfffffff0;
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/* TODO: On SR56x0/SP5100 board, the IOAPIC on SR56x0 is the
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* 2nd one. We need to check if it also is on your board. */
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setup_ioapic((void *)dword, 1);
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}
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static void pcie_init(struct device *dev)
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{
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/* Enable pci error detecting */
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u32 dword;
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printk(BIOS_INFO, "pcie_init in sr5650_ht.c\n");
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/* System error enable */
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dword = pci_read_config32(dev, 0x04);
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dword |= (1 << 8); /* System error enable */
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dword |= (1 << 30); /* Clear possible errors */
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pci_write_config32(dev, 0x04, dword);
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/*
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* 1 is APIC enable
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* 18 is enable nb to accept A4 interrupt request from SB.
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*/
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dword = pci_read_config32(dev, 0x4C);
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dword |= 1 << 1 | 1 << 18; /* Clear possible errors */
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pci_write_config32(dev, 0x4C, dword);
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sr5690_apic_init(dev);
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}
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static void sr5690_read_resource(struct device *dev)
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{
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if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
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printk(BIOS_DEBUG,"%s: %s\n", __func__, dev_path(dev));
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set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */
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}
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pci_dev_read_resources(dev);
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/* rpr6.2.(1). Write the Base Address Register (BAR) */
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pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */
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pci_get_resource(dev, 0xfc); /* APIC located in sr5690 */
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compact_resources(dev);
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}
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/* If IOAPIC's index changes, we should replace the pci_dev_set_resource(). */
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static void sr5690_set_resources(struct device *dev)
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{
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pci_write_config32(dev, 0xf8, 0x1); /* Set IOAPIC's index to 1 and make sure no one changes it */
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if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
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uint32_t reg;
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device_t amd_ht_cfg_dev;
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device_t amd_addr_map_dev;
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resource_t res_base;
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resource_t res_end;
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uint32_t base;
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uint32_t limit;
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struct resource *res;
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printk(BIOS_DEBUG,"%s %s\n", dev_path(dev), __func__);
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/* Find requisite AMD CPU devices */
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amd_ht_cfg_dev = dev_find_slot(0, PCI_DEVFN(0x18, 0));
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amd_addr_map_dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
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if (!amd_ht_cfg_dev || !amd_addr_map_dev) {
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printk(BIOS_WARNING, "%s: %s Unable to locate CPU control devices\n", __func__, dev_path(dev));
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} else {
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res = sr5650_retrieve_cpu_mmio_resource();
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if (res) {
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/* Set up MMCONFIG bus range */
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set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 0 << 3); /* Make BAR3 visible */
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set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 1 << 30); /* Enables writes to the BAR3 register */
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set_nbcfg_enable_bits(dev, 0x84, 7 << 16, 0 << 16); /* Program bus range = 255 busses */
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pci_write_config32(dev, 0x1c, res->base);
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/* Enable MMCONFIG decoding. */
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set_htiu_enable_bits(dev, 0x32, 1 << 28, 1 << 28); /* PCIEMiscInit */
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set_nbcfg_enable_bits(dev, 0x7c, 1 << 30, 0 << 30); /* Disable writes to the BAR3 register */
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set_nbmisc_enable_bits(dev, 0x0, 1 << 3, 1 << 3); /* Hide BAR3 */
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/* Set up nonposted resource in MMIO space */
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res_base = res->base; /* Get the base address */
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res_end = resource_end(res); /* Get the limit (rounded up) */
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printk(BIOS_DEBUG, "%s: %s[0x1c] base = %0llx limit = %0llx\n", __func__, dev_path(dev), res_base, res_end);
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/* Locate an unused MMIO resource */
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for (reg = 0xb8; reg >= 0x80; reg -= 8) {
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base = pci_read_config32(amd_addr_map_dev, reg);
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limit = pci_read_config32(amd_addr_map_dev, reg + 4);
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if (!(base & 0x3))
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break; /* Unused resource found */
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}
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/* If an unused MMIO resource was available, set up the mapping */
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if (!(base & 0x3)) {
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uint32_t sblk;
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/* Remember this resource has been stored. */
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res->flags |= IORESOURCE_STORED;
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report_resource_stored(dev, res, " <mmconfig>");
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/* Get SBLink value (HyperTransport I/O Hub Link ID). */
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sblk = (pci_read_config32(amd_ht_cfg_dev, 0x64) >> 8) & 0x3;
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/* Calculate the MMIO mapping base */
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base &= 0x000000f0;
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base |= ((res_base >> 8) & 0xffffff00);
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base |= 3;
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/* Calculate the MMIO mapping limit */
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limit &= 0x00000048;
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limit |= ((res_end >> 8) & 0xffffff00);
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limit |= (sblk << 4);
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limit |= (1 << 7);
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/* Configure and enable MMIO mapping */
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printk(BIOS_INFO, "%s: %s <- index %x base %04x limit %04x\n", __func__, dev_path(amd_addr_map_dev), reg, base, limit);
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pci_write_config32(amd_addr_map_dev, reg + 4, limit);
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pci_write_config32(amd_addr_map_dev, reg, base);
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}
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else {
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printk(BIOS_WARNING, "%s: %s No free MMIO resources available\n", __func__, dev_path(dev));
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}
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} else {
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printk(BIOS_WARNING, "%s: %s Unable to locate CPU MMCONF resource\n", __func__, dev_path(dev));
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}
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}
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}
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pci_dev_set_resources(dev);
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}
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static struct pci_operations lops_pci = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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static struct device_operations ht_ops = {
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.read_resources = sr5690_read_resource,
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.set_resources = sr5690_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = pcie_init,
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.scan_bus = 0,
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.ops_pci = &lops_pci,
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};
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static const struct pci_driver ht_driver_sr5690 __pci_driver = {
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.ops = &ht_ops,
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.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_AMD_SR5690_HT,
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};
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static const struct pci_driver ht_driver_sr5670 __pci_driver = {
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.ops = &ht_ops,
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.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_AMD_SR5670_HT,
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};
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static const struct pci_driver ht_driver_sr5650 __pci_driver = {
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.ops = &ht_ops,
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.vendor = PCI_VENDOR_ID_ATI,
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.device = PCI_DEVICE_ID_AMD_SR5650_HT,
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};
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