26679699cd
Enable P2SB in static device tree so that hide/unhide trick works. Change-Id: I7dc20b001605b715155d333a07580e21a5f24136 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
54 lines
1.2 KiB
Text
54 lines
1.2 KiB
Text
chip soc/intel/xeon_sp/cpx
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host bridge
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device pci 04.0 on end
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device pci 04.1 on end
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device pci 04.2 on end
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device pci 04.3 on end
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device pci 04.4 on end
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device pci 04.5 on end
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device pci 04.6 on end
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device pci 04.7 on end
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device pci 05.0 on end
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device pci 05.2 on end
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device pci 05.4 on end
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device pci 08.0 on end
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device pci 08.1 on end
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device pci 08.2 on end
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device pci 11.0 on end
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device pci 11.1 on end
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device pci 11.5 on end
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device pci 14.0 on end
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device pci 16.0 on end
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device pci 16.1 on end
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device pci 16.4 on end
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device pci 17.0 on end
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device pci 1c.0 on end
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device pci 1c.4 on end
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device pci 1f.1 on end
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device pci 1f.2 on end
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device pci 1f.4 on end
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device pci 1f.5 on end
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device pci 1f.0 on # LPC/eSPI Interface
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chip superio/common
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device pnp 2e.0 on
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chip superio/aspeed/ast2400
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register "use_espi" = "1"
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device pnp 2e.2 on # SUART1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # SUART2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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end
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end
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end
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end
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end
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end
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