33e5df3f25
PCI bus operations are static through the ramstage, and should be initialized from the very beginning. For all the replaced instances, there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for the northbridge, so these continue to use PCI IO config access. Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/3607 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> |
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|---|---|---|
| .. | ||
| acpi | ||
| acpi_tables.c | ||
| cache_as_ram.inc | ||
| cmos.layout | ||
| devicetree.cb | ||
| dsdt.asl | ||
| fw_cfg.c | ||
| fw_cfg.h | ||
| fw_cfg_if.h | ||
| irq_tables.c | ||
| Kconfig | ||
| mainboard.c | ||
| Makefile.inc | ||
| memory.c | ||
| northbridge.c | ||
| romstage.c | ||