a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
167 lines
4.4 KiB
Text
167 lines
4.4 KiB
Text
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 secunet Security Networks AG
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/* =================== Generic PnP Device =================== */
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/*
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* Generic setup for PnP devices.
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*
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* Controlled by the following preprocessor defines:
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*
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* SUPERIO_CHIP_NAME The name of the super i/o chip (unique, required)
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* SUPERIO_PNP_LDN The logical device number on the super i/o
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* chip for this device (required)
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* SUPERIO_PNP_DDN A string literal that identifies the dos device
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* name (DDN) of this device (e.g. "COM1", optional)
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* SUPERIO_PNP_PM_REG Identifier of a 1-bit register to power down
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* the logical device (optional)
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* SUPERIO_PNP_PM_VAL The value for SUPERIO_PNP_PM_REG to power the logical
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* device down (required if SUPERIO_PNP_PM_REG is defined)
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* SUPERIO_PNP_PM_LDN The logical device number to access the PM_REG
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* bit (required if SUPERIO_PNP_PM_REG is defined)
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* SUPERIO_PNP_IO0 The alignment and length of the first PnP i/o
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* resource (comma seperated, e.g. `0x02, 0x08`,
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* optional)
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* SUPERIO_PNP_IO1 The alignment and length of the second PnP i/o
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* resource (comma seperated, e.g. `0x02, 0x08`,
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* optional)
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* SUPERIO_PNP_IRQ0 If defined, the first PnP IRQ register is enabled
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* SUPERIO_PNP_IRQ1 If defined, the second PnP IRQ register is enabled
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* SUPERIO_PNP_DMA If defined, the PnP DMA register is enabled
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*/
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#include "pnp.asl"
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#ifndef SUPERIO_CHIP_NAME
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# error "SUPERIO_CHIP_NAME is not defined."
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#endif
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#ifndef SUPERIO_PNP_LDN
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# error "SUPERIO_PNP_LDN is not defined."
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#endif
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Device (SUPERIO_ID(PN, SUPERIO_PNP_LDN)) {
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Name (_HID, EisaId ("PNP0c02")) /* TODO: Better fitting EisaId? */
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Name (_UID, SUPERIO_UID(PN, SUPERIO_PNP_LDN))
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#ifdef SUPERIO_PNP_DDN
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Name (_DDN, SUPERIO_PNP_DDN)
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#endif
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Method (_STA)
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{
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PNP_GENERIC_STA(SUPERIO_PNP_LDN)
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}
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Method (_DIS)
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{
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PNP_GENERIC_DIS(SUPERIO_PNP_LDN)
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}
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#ifdef SUPERIO_PNP_PM_REG
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Method (_PSC) {
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PNP_GENERIC_PSC(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN)
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}
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Method (_PS0) {
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PNP_GENERIC_PS0(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN)
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}
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Method (_PS1) {
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PNP_GENERIC_PS1(SUPERIO_PNP_PM_REG, SUPERIO_PNP_PM_VAL, SUPERIO_PNP_PM_LDN)
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}
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#else
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Method (_PSC) {
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PNP_DEFAULT_PSC
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}
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#endif
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Method (_CRS)
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{
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Name (CRS, ResourceTemplate () {
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#ifdef SUPERIO_PNP_IO0
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IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO0, IO0)
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#endif
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#ifdef SUPERIO_PNP_IO1
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IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1)
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#endif
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#ifdef SUPERIO_PNP_IRQ0
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IRQNoFlags (IR0) {}
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#endif
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#ifdef SUPERIO_PNP_IRQ1
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IRQNoFlags (IR1) {}
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#endif
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#ifdef SUPERIO_PNP_DMA
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DMA (Compatibility, NotBusMaster, Transfer8, DM0) {}
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#endif
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})
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ENTER_CONFIG_MODE (SUPERIO_PNP_LDN)
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#ifdef SUPERIO_PNP_IO0
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PNP_READ_IO(PNP_IO0, CRS, IO0)
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#endif
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#ifdef SUPERIO_PNP_IO1
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PNP_READ_IO(PNP_IO1, CRS, IO1)
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#endif
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#ifdef SUPERIO_PNP_IRQ0
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PNP_READ_IRQ(PNP_IRQ0, CRS, IR0)
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#endif
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#ifdef SUPERIO_PNP_IRQ1
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PNP_READ_IRQ(PNP_IRQ1, CRS, IR1)
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#endif
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#ifdef SUPERIO_PNP_DMA
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PNP_READ_DMA(PNP_DMA0, CRS, DM0)
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#endif
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EXIT_CONFIG_MODE ()
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Return (CRS)
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}
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Method (_SRS, 1, Serialized)
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{
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Name (TMPL, ResourceTemplate () {
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#ifdef SUPERIO_PNP_IO0
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IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO0, IO0)
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#endif
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#ifdef SUPERIO_PNP_IO1
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IO (Decode16, 0x0000, 0x0000, SUPERIO_PNP_IO1, IO1)
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#endif
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#ifdef SUPERIO_PNP_IRQ0
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IRQNoFlags (IR0) {}
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#endif
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#ifdef SUPERIO_PNP_IRQ1
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IRQNoFlags (IR1) {}
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#endif
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#ifdef SUPERIO_PNP_DMA
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DMA (Compatibility, NotBusMaster, Transfer8, DM0) {}
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#endif
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})
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ENTER_CONFIG_MODE (SUPERIO_PNP_LDN)
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#ifdef SUPERIO_PNP_IO0
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PNP_WRITE_IO(PNP_IO0, Arg0, IO0)
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#endif
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#ifdef SUPERIO_PNP_IO1
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PNP_WRITE_IO(PNP_IO1, Arg0, IO1)
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#endif
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#ifdef SUPERIO_PNP_IRQ0
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PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0)
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#endif
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#ifdef SUPERIO_PNP_IRQ1
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PNP_WRITE_IRQ(PNP_IRQ1, Arg0, IR1)
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#endif
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#ifdef SUPERIO_PNP_DMA
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PNP_WRITE_DMA(PNP_DMA0, Arg0, DM0)
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#endif
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Store (One, PNP_DEVICE_ACTIVE)
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EXIT_CONFIG_MODE ()
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}
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}
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