82ba4d092b
BUG=chrome-os-partner:29778 TEST=Build coreboot Change-Id: I4c1864171e56a81e8eda95a15ca6a6bc1adc7a70 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 814af4b653432295cb6d7222af4a6e5a8d9dfbf6 Original-Change-Id: I1a986fbc8b3737bae655207dd89865dd39aecf87 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/209467 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Commit-Queue: Lin Huang <hl@rock-chips.com> Original-Tested-by: Lin Huang <hl@rock-chips.com> Reviewed-on: http://review.coreboot.org/8866 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins)
63 lines
1.5 KiB
C
63 lines
1.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright 2014 Rockchip Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdlib.h>
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#include <string.h>
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#include <stddef.h>
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#include <delay.h>
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#include <console/console.h>
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#include <device/device.h>
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#include <cbmem.h>
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#include <arch/cache.h>
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#include <soc/rockchip/rk3288/gpio.h>
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#include "soc.h"
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#include "chip.h"
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static void soc_enable(device_t dev)
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{
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ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB);
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}
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static void soc_init(device_t dev)
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{
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}
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static void soc_noop(device_t dev)
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{
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}
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static struct device_operations soc_ops = {
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.read_resources = soc_noop,
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.set_resources = soc_noop,
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.enable_resources = soc_enable,
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.init = soc_init,
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.scan_bus = 0,
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};
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static void enable_rk3288_dev(device_t dev)
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{
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dev->ops = &soc_ops;
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}
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struct chip_operations soc_rockchip_rk3288_ops = {
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CHIP_NAME("SOC Rockchip 3288")
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.enable_dev = enable_rk3288_dev,
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};
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