13f66507af
MMIO operations are arch-agnostic so the include path should not be arch/. Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/31691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
313 lines
8.5 KiB
C
313 lines
8.5 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <device/mmio.h>
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#include <device/pci.h>
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#include <soc/gpio.h>
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#include <soc/pm.h>
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#include <soc/smm.h>
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#define GPIO_DEBUG
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/* gpio map to pad number LUTs */
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static const u8 gpncommunity_gpio_to_pad[GP_NORTH_COUNT] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 15,
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16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
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26, 27, 30, 31, 32, 33, 34, 35, 36, 37,
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38, 39, 40, 41, 45, 46, 47, 48, 49, 50,
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51, 52, 53, 54, 55, 56, 60, 61, 62, 63,
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64, 65, 66, 67, 68, 69, 70, 71, 72 };
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static const u8 gpsecommunity_gpio_to_pad[GP_SOUTHEAST_COUNT] = {
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0, 1, 2, 3, 4, 5, 6, 7, 15, 16,
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17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
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30, 31, 32, 33, 34, 35, 45, 46, 47, 48,
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49, 50, 51, 52, 60, 61, 62, 63, 64, 65,
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66, 67, 68, 69, 75, 76, 77, 78, 79, 80,
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81, 82, 83, 84, 85 };
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static const u8 gpswcommunity_gpio_to_pad[GP_SOUTHWEST_COUNT] = {
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0, 1, 2, 3, 4, 5, 6, 7, 15, 16,
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17, 18, 19, 20, 21, 22, 30, 31, 32, 33,
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34, 35, 36, 37, 45, 46, 47, 48, 49, 50,
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51, 52, 60, 61, 62, 63, 64, 65, 66, 67,
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75, 76, 77, 78, 79, 80, 81, 82, 90, 91,
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92, 93, 94, 95, 96, 97 };
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static const u8 gpecommunity_gpio_to_pad[GP_EAST_COUNT] = {
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
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10, 11, 15, 16, 17, 18, 19, 20, 21, 22,
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23, 24, 25, 26 };
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/* GPIO Community descriptions */
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static const struct gpio_bank gpnorth_community = {
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.gpio_count = GP_NORTH_COUNT,
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.gpio_to_pad = gpncommunity_gpio_to_pad,
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.pad_base = COMMUNITY_GPNORTH_BASE,
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.has_gpe_en = GPE_CAPABLE,
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.has_wake_en = 1,
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};
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static const struct gpio_bank gpsoutheast_community = {
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.gpio_count = GP_SOUTHEAST_COUNT,
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.gpio_to_pad = gpsecommunity_gpio_to_pad,
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.pad_base = COMMUNITY_GPSOUTHEAST_BASE,
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.has_gpe_en = GPE_CAPABLE_NONE,
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.has_wake_en = 1,
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};
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static const struct gpio_bank gpsouthwest_community = {
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.gpio_count = GP_SOUTHWEST_COUNT,
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.gpio_to_pad = gpswcommunity_gpio_to_pad,
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.pad_base = COMMUNITY_GPSOUTHWEST_BASE,
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.has_gpe_en = GPE_CAPABLE,
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.has_wake_en = 1,
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};
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static const struct gpio_bank gpeast_community = {
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.gpio_count = GP_EAST_COUNT,
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.gpio_to_pad = gpecommunity_gpio_to_pad,
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.pad_base = COMMUNITY_GPEAST_BASE,
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.has_gpe_en = GPE_CAPABLE_NONE,
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.has_wake_en = 1,
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};
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static void setup_gpio_route(const struct soc_gpio_map *sw_gpios,
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const struct soc_gpio_map *n_gpios)
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{
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const struct soc_gpio_map *n_config;
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const struct soc_gpio_map *sw_config;
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uint32_t route_reg = 0;
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uint32_t int_selection = 0;
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uint32_t alt_gpio_smi = 0;
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uint32_t gpe0a_en = 0;
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int gpio = 0;
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int north_done = 0;
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int south_done = 0;
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for (sw_config = sw_gpios, n_config = n_gpios;
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(!north_done || !south_done); sw_config++, n_config++, gpio++) {
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/* when north config is done */
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if ((gpio > GP_NORTH_COUNT) ||
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(n_config->pad_conf0 == GPIO_LIST_END))
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north_done = 1;
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/* when sw is done */
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if ((gpio > GP_SOUTHWEST_COUNT) ||
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(sw_config->pad_conf0 == GPIO_LIST_END))
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south_done = 1;
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/* route north gpios */
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if (!north_done) {
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/* Int select from 8 to 15 */
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int_selection = ((n_config->pad_conf0 >> 28) & 0xf);
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if (n_config->gpe == SMI) {
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/*
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* Set the corresponding bits (01) as
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* per the interrupt line
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*/
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route_reg |= (1 << ((int_selection - 8) * 2));
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/* reset the higher bit */
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route_reg &=
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~(1 << ((int_selection - 8) * 2 + 1));
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alt_gpio_smi |= (1 << (int_selection + 8));
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} else if (n_config->gpe == SCI) {
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/*
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* Set the corresponding bits as per the
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* interrupt line
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*/
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route_reg |=
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(1 << (((int_selection - 8) * 2) + 1));
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/* reset the bit */
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route_reg &= ~(1 << ((int_selection - 8) * 2));
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gpe0a_en |= (1 << (int_selection + 8));
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}
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}
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/* route southwest gpios */
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if (!south_done) {
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/* Int select from 8 to 15 */
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int_selection = ((sw_config->pad_conf0 >> 28) & 0xf);
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if (sw_config->gpe == SMI) {
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/*
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* Set the corresponding bits (10) as
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* per the interrupt line
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*/
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route_reg |= (1 << (int_selection * 2));
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route_reg &= ~(1 << (int_selection * 2 + 1));
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alt_gpio_smi |= (1 << (int_selection + 16));
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} else if (sw_config->gpe == SCI) {
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/*
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* Set the corresponding bits as
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* per the interrupt line
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*/
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route_reg |= (1 << ((int_selection * 2) + 1));
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/* reset the bit */
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route_reg &= ~(1 << (int_selection * 2));
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gpe0a_en |= (1 << (int_selection + 16));
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}
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}
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}
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/* enable gpe bits in GPE0A_EN_REG */
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outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0A_EN_REG);
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#ifdef GPIO_DEBUG
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printk(BIOS_DEBUG, "gpio_rout = %x alt_gpio_smi = %x gpe0a_en = %x\n",
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route_reg, alt_gpio_smi, gpe0a_en);
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#endif
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/* Save as an smm param */
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southcluster_smm_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
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}
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static void setup_gpios(const struct soc_gpio_map *gpios,
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const struct gpio_bank *community)
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{
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const struct soc_gpio_map *config;
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int gpio = 0;
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u32 reg, family, internal_pad_num;
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u32 mmio_addr, int_selection;
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u32 gpio_wake0 = 0;
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u32 gpio_wake1 = 0;
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u32 gpio_int_mask = 0;
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if (!gpios)
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return;
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for (config = gpios; config->pad_conf0 != GPIO_LIST_END;
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config++, gpio++) {
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if (gpio > community->gpio_count)
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break;
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/* Pad configuration registers */
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family = community->gpio_to_pad[gpio] / MAX_FAMILY_PAD_GPIO_NO;
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internal_pad_num = community->gpio_to_pad[gpio] %
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MAX_FAMILY_PAD_GPIO_NO;
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/*
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* Calculate the MMIO Address for specific GPIO pin
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* control register pointed by index.
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* REG = (IOBASE + COMMUNITY_BASE + (0X04400)) +
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* (0X400*FAMILY_NUM) + (8 * PAD_NUM)
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*/
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mmio_addr = FAMILY_PAD_REGS_OFF
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+ (FAMILY_PAD_REGS_SIZE * family)
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+ (GPIO_REGS_SIZE * internal_pad_num);
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reg = community->pad_base + mmio_addr;
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/* get int selection value */
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int_selection = ((config->pad_conf0 >> 28) & 0xf);
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/* get int mask register value */
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gpio_int_mask |= (config->int_mask << int_selection);
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/*
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* wake capable programming
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* some communities have 2 wake regs
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*/
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if (gpio > 31)
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gpio_wake1 |= config->wake_mask << (gpio % 32);
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else
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gpio_wake0 |= config->wake_mask << gpio;
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if (!config->skip_config) {
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#ifdef GPIO_DEBUG
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printk(BIOS_DEBUG,
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"Write Pad: Base(%x) - conf0 = %x conf1= %x gpio #- %d pad # = %d\n",
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reg, config->pad_conf0, config->pad_conf1,
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community->gpio_to_pad[gpio], gpio);
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#endif
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/*
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* write pad configurations to conf0 and conf1 register
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*/
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write32((void *)(reg + PAD_CONF0_REG),
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config->pad_conf0);
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write32((void *)(reg + PAD_CONF1_REG),
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config->pad_conf1);
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}
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}
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#ifdef GPIO_DEBUG
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printk(BIOS_DEBUG,
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"gpio_wake_mask0 = %x gpio_wake_mask1 = %x gpio_int_mask = %x\n",
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gpio_wake0, gpio_wake1, gpio_int_mask);
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#endif
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/* Wake */
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write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0),
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gpio_wake0);
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/* wake mask config for communities with 2 regs */
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if (community->gpio_count > 32)
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write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1),
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gpio_wake1);
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/* Interrupt */
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write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK),
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gpio_int_mask);
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}
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void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
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{
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if (config) {
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/*
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* Write the default value 0xffffff to the SW
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* write_access_policy_interrupt_reg to allow the SW interrupt
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* mask register to be set
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*/
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write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108),
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0xffffffff);
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printk(BIOS_DEBUG, "north\n");
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setup_gpios(config->north, &gpnorth_community);
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printk(BIOS_DEBUG, "southwest\n");
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setup_gpios(config->southwest, &gpsouthwest_community);
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printk(BIOS_DEBUG, "southeast\n");
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setup_gpios(config->southeast, &gpsoutheast_community);
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printk(BIOS_DEBUG, "east\n");
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setup_gpios(config->east, &gpeast_community);
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printk(BIOS_DEBUG, "Routing SW and N gpios\n");
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setup_gpio_route(config->southwest, config->north);
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}
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/*
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* Set on die termination feature with pull up value and
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* drive the pad high for TAP_TDO and TAP_TMS
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*/
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if (!enable_xdp_tap)
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printk(BIOS_DEBUG, "Tri-state TDO and TMS\n");
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}
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__weak struct soc_gpio_config *mainboard_get_gpios(void)
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{
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printk(BIOS_DEBUG, "Default/empty GPIO config\n");
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return NULL;
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}
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