87 lines
2.7 KiB
C
87 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <device/pci_ops.h>
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#include <soc/acpi.h>
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#include <soc/ramstage.h>
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unsigned long acpi_fill_madt(unsigned long current)
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{
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return current;
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}
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unsigned long acpi_fill_mcfg(unsigned long current)
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{
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return current;
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}
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void acpi_fill_fadt(acpi_fadt_t *fadt)
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{
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struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC,
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PCI_FUNCTION_NUMBER_QNC_LPC);
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uint32_t gpe0_base = pci_read_config32(dev, R_QNC_LPC_GPE0BLK)
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& B_QNC_LPC_GPE0BLK_MASK;
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uint32_t pmbase = pci_read_config32(dev, R_QNC_LPC_PM1BLK)
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& B_QNC_LPC_PM1BLK_MASK;
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fadt->flags |= ACPI_FADT_PLATFORM_CLOCK;
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/* PM1 Status: ACPI 4.8.3.1.1 */
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fadt->pm1a_evt_blk = pmbase + R_QNC_PM1BLK_PM1S;
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fadt->pm1_evt_len = 2;
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fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
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fadt->x_pm1a_evt_blk.bit_offset = 0;
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fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_evt_blk.addrl = pmbase + R_QNC_PM1BLK_PM1S;
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fadt->x_pm1a_evt_blk.addrh = 0x0;
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/* PM1 Control: ACPI 4.8.3.2.1 */
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fadt->pm1a_cnt_blk = pmbase + R_QNC_PM1BLK_PM1C;
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fadt->pm1_cnt_len = 2;
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fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
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fadt->x_pm1a_cnt_blk.bit_offset = 0;
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fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
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fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
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fadt->x_pm1a_cnt_blk.addrh = 0x0;
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/* PM Timer: ACPI 4.8.3.3 */
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fadt->pm_tmr_blk = pmbase + R_QNC_PM1BLK_PM1T;
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fadt->pm_tmr_len = 4;
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fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
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fadt->x_pm_tmr_blk.bit_offset = 0;
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fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
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fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
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fadt->x_pm_tmr_blk.addrh = 0x0;
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/* General-Purpose Event 0 Registers: ACPI 4.8.4.1 */
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fadt->gpe0_blk = gpe0_base;
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fadt->gpe0_blk_len = 4 * 2;
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fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
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fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
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fadt->x_gpe0_blk.bit_offset = 0;
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fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
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fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
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fadt->x_gpe0_blk.addrh = 0;
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/* Display the base registers */
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printk(BIOS_SPEW, "FADT:\n");
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printk(BIOS_SPEW, " 0x%08x: GPE0_BASE\n", gpe0_base);
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printk(BIOS_SPEW, " 0x%08x: PMBASE\n", pmbase);
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printk(BIOS_SPEW, " 0x%08x: RESET\n", fadt->reset_reg.addrl);
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}
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uint16_t get_pmbase(void)
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{
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struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC,
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PCI_FUNCTION_NUMBER_QNC_LPC);
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return (uint16_t) pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK;
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}
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