bd4af105c4
`fsp/util.h` draws incompatible UDK headers in. Hence, we have to declare it locally again. Change-Id: Iaa5981088eeb5c36f765d6332ae47a38a6a4c875 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40729 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
78 lines
2.2 KiB
C
78 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <commonlib/helpers.h>
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#include <console/console.h>
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#include <device/mmio.h>
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#include <device/resource.h>
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#include <drivers/intel/gma/i915.h>
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#include <drivers/intel/gma/i915_reg.h>
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#include <intelblocks/graphics.h>
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#include <soc/ramstage.h>
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#include <types.h>
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void graphics_soc_init(struct device *dev)
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{
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struct soc_intel_skylake_config *conf = config_of(dev);
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struct resource *mmio_res;
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uint8_t *base;
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u32 reg32;
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if (!conf)
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return;
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mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0);
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if (!mmio_res || !mmio_res->base)
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return;
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base = (void *)(uintptr_t)mmio_res->base;
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reg32 = conf->gpu_pp_up_delay_ms * 10 << 16;
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reg32 |= conf->gpu_pp_backlight_on_delay_ms * 10;
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write32(base + PCH_PP_ON_DELAYS, reg32);
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reg32 = conf->gpu_pp_down_delay_ms * 10 << 16;
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reg32 |= conf->gpu_pp_backlight_off_delay_ms * 10;
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write32(base + PCH_PP_OFF_DELAYS, reg32);
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reg32 = read32(base + PCH_PP_DIVISOR);
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reg32 &= ~0x1f;
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reg32 |= (DIV_ROUND_UP(conf->gpu_pp_cycle_delay_ms, 100) + 1) & 0x1f;
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write32(base + PCH_PP_DIVISOR, reg32);
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/* So far all devices seem to use the PCH PWM function.
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The CPU PWM registers are all zero after reset. */
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if (conf->gpu_pch_backlight_pwm_hz) {
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/* Reference clock is 24MHz. We can choose either a 16
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or a 128 step increment. Use 16 if we would have less
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than 100 steps otherwise. */
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const unsigned int hz_limit = 24 * 1000 * 1000 / 128 / 100;
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unsigned int pwm_increment, pwm_period;
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u32 south_chicken1;
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south_chicken1 = read32(base + SOUTH_CHICKEN1);
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if (conf->gpu_pch_backlight_pwm_hz > hz_limit) {
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pwm_increment = 16;
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south_chicken1 &= ~1;
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} else {
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pwm_increment = 128;
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south_chicken1 |= 1;
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}
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write32(base + SOUTH_CHICKEN1, south_chicken1);
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pwm_period = 24 * 1000 * 1000 / pwm_increment
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/ conf->gpu_pch_backlight_pwm_hz;
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/* Start with a 50% duty cycle. */
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write32(base + BLC_PWM_PCH_CTL2,
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pwm_period << 16 | pwm_period / 2);
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write32(base + BLC_PWM_PCH_CTL1,
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!!conf->gpu_pch_backlight_polarity << 29 |
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BLM_PCH_PWM_ENABLE);
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}
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}
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const struct i915_gpu_controller_info *
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intel_igd_get_controller_info(const struct device *device)
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{
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struct soc_intel_skylake_config *chip = device->chip_info;
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return &chip->gfx;
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}
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