6b5bc77c9b
Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. */") -# This file is part of a set of unofficial pre-commit hooks available -/* This file is part of coreboot */ -# This file is part of msrtool. -/* This file is part of msrtool. */ - * This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. */ - * This file is part of the coreboot project. - /* This file is part of the coreboot project. */ -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/* This file is part of the coreboot project */ -/* This file is part of the coreboot project. */ -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - * This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. */ -/* This file is part of the ectool project. */ - * This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. */ -## This file is part of the superiotool project. -/* This file is part of the superiotool project */ -/* This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
102 lines
2.4 KiB
C
102 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <bootblock_common.h>
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#include <stdint.h>
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#include <cf9_reset.h>
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#include <device/pnp_ops.h>
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#include <superio/winbond/common/winbond.h>
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#include <superio/winbond/w83627dhg/w83627dhg.h>
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#include <console/console.h>
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#include <northbridge/intel/i945/i945.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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#include <cpu/x86/msr.h>
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#include <cpu/intel/speedstep.h>
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#include <arch/cpu.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
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/*
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* BSEL0 is connected with GPIO32
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* BSEL1 is connected with GPIO33 with inversed logic
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* BSEL2 is connected with GPIO55
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*/
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static int setup_sio_gpio(u8 bsel)
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{
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int need_reset = 0;
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u8 reg, old_reg;
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pnp_enter_ext_func_mode(GPIO_DEV);
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pnp_set_logical_device(GPIO_DEV);
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reg = 0x9a;
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old_reg = pnp_read_config(GPIO_DEV, 0x2c);
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pnp_write_config(GPIO_DEV, 0x2c, reg);
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need_reset = (reg != old_reg);
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pnp_write_config(GPIO_DEV, 0x30, 0x0e);
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pnp_write_config(GPIO_DEV, 0xe0, 0xde);
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pnp_write_config(GPIO_DEV, 0xf0, 0xf3);
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pnp_write_config(GPIO_DEV, 0xf4, 0x80);
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pnp_write_config(GPIO_DEV, 0xf5, 0x80);
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/* Invert GPIO33 */
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pnp_write_config(GPIO_DEV, 0xf2, 0x08);
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reg = (bsel & 3) << 2;
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old_reg = pnp_read_config(GPIO_DEV, 0xf1);
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pnp_write_config(GPIO_DEV, 0xf1, reg);
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need_reset += ((reg & 0xc) != (old_reg & 0xc));
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reg = (bsel >> 2) << 5;
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old_reg = pnp_read_config(GPIO_DEV, 0xe1);
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pnp_write_config(GPIO_DEV, 0xe1, reg);
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need_reset += ((reg & 0x20) != (old_reg & 0x20));
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pnp_exit_ext_func_mode(GPIO_DEV);
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return need_reset;
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}
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static u8 msr_get_fsb(void)
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{
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u8 fsbcfg;
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msr_t msr;
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const u32 eax = cpuid_eax(1);
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/* Netburst */
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if (((eax >> 8) & 0xf) == 0xf) {
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msr = rdmsr(MSR_EBC_FREQUENCY_ID);
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fsbcfg = (msr.lo >> 16) & 0x7;
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} else { /* Intel Core 2 */
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msr = rdmsr(MSR_FSB_FREQ);
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fsbcfg = msr.lo & 0x7;
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}
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return fsbcfg;
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}
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void mainboard_late_rcba_config(void)
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{
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/* Enable only PCIe Root Port Clock Gate */
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RCBA32(CG) = 0x00000001;
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}
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void mainboard_pre_raminit_config(int s3_resume)
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{
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u8 c_bsel = msr_get_fsb();
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/*
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* Result is that FSB is incorrect on s3 resume (fixed at 800MHz).
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* Some CPU accept this others don't.
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*/
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if (!s3_resume && setup_sio_gpio(c_bsel)) {
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printk(BIOS_DEBUG,
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"Needs reset to configure CPU BSEL straps\n");
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full_reset();
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}
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}
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void bootblock_mainboard_early_init(void)
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{
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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