93375f270c
Explain why the flash is no longer cached. BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibb18f363a215d665d53a722ed76896a75d1c5608 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42108 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
128 lines
3.2 KiB
C
128 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cpu/cpu.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/msr.h>
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#include <cpu/x86/smm.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/amd64_save_state.h>
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#include <cpu/x86/lapic.h>
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#include <device/device.h>
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#include <device/pci_ops.h>
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#include <soc/pci_devs.h>
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#include <soc/cpu.h>
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#include <soc/reset.h>
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#include <soc/smi.h>
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#include <soc/iomap.h>
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#include <console/console.h>
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/*
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* MP and SMM loading initialization.
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*/
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struct smm_relocation_params {
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msr_t tseg_base;
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msr_t tseg_mask;
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};
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static struct smm_relocation_params smm_reloc_params;
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/*
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* Do essential initialization tasks before APs can be fired up -
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*
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* 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This
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* creates the MTRR solution that the APs will use. Otherwise APs will try to
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* apply the incomplete solution as the BSP is calculating it.
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*/
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static void pre_mp_init(void)
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{
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x86_setup_mtrrs_with_detect();
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x86_mtrr_check();
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}
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int get_cpu_count(void)
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{
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return 1 + (cpuid_ecx(0x80000008) & 0xff);
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}
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static void fill_in_relocation_params(struct smm_relocation_params *params)
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{
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uintptr_t tseg_base;
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size_t tseg_size;
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smm_region(&tseg_base, &tseg_size);
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params->tseg_base.lo = ALIGN_DOWN(tseg_base, 128 * KiB);
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params->tseg_base.hi = 0;
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params->tseg_mask.lo = ALIGN_DOWN(~(tseg_size - 1), 128 * KiB);
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params->tseg_mask.hi = ((1 << (cpu_phys_address_size() - 32)) - 1);
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params->tseg_mask.lo |= SMM_TSEG_WB;
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}
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static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
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size_t *smm_save_state_size)
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{
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printk(BIOS_DEBUG, "Setting up SMI for CPU\n");
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fill_in_relocation_params(&smm_reloc_params);
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smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);
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*smm_save_state_size = sizeof(amd64_smm_state_save_area_t);
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}
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static void relocation_handler(int cpu, uintptr_t curr_smbase,
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uintptr_t staggered_smbase)
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{
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struct smm_relocation_params *relo_params = &smm_reloc_params;
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amd64_smm_state_save_area_t *smm_state;
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wrmsr(SMM_ADDR_MSR, relo_params->tseg_base);
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wrmsr(SMM_MASK_MSR, relo_params->tseg_mask);
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smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase);
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smm_state->smbase = staggered_smbase;
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}
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static const struct mp_ops mp_ops = {
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.pre_mp_init = pre_mp_init,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = get_smm_info,
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.relocation_handler = relocation_handler,
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.post_mp_init = enable_smi_generation,
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};
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void mp_init_cpus(struct bus *cpu_bus)
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{
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/* Clear for take-off */
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if (mp_init_with_smm(cpu_bus, &mp_ops) < 0)
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printk(BIOS_ERR, "MP initialization failure.\n");
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/* pre_mp_init made the flash not cacheable. Reset to WP for performance. */
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mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
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set_warm_reset_flag();
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}
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static void model_17_init(struct device *dev)
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{
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check_mca();
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setup_lapic();
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}
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static struct device_operations cpu_dev_ops = {
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.init = model_17_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, PICASSO_B0_CPUID },
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{ X86_VENDOR_AMD, PICASSO_B1_CPUID },
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{ X86_VENDOR_AMD, RAVEN2_A0_CPUID },
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{ X86_VENDOR_AMD, RAVEN2_A1_CPUID },
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{ 0, 0 },
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};
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static const struct cpu_driver model_17 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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