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Vadim Bendebury 93649b122e google/gru: Determine Board ID based on the input voltage of ADC1
The Board ID on the Gru family of boards is determined by reading the
voltage from a resistor divider, each hardware revision is supposed to
have a unique resistor ratio, which allows to distinctly tell between
different Board ID.

While the long time approach to mapping resistor ratios (and voltages)
into Board ID remains under discussion, we know for sure the values
for Proto 1 and Proto 2. Let's just use them for now.

Since Board ID can be queried multiple times during boot, ideally it
should be read once and placed in the coreboot table to be available
to all coreboot stages. For now we just cache it so that at least
during the same stage the ADC has to run only once.

BRANCH=None
BUG=chrome-os-partner:51537
TEST=verified that the voltage reading on Proto 1 is as expected, and
     Board ID 0 is reported.

Change-Id: I94bc7fc235dae4155feb6ca35b5ef0ab20c3ec9c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb4064d0af8174b6ae247cdad9378b7f4e5f22ba
Original-Change-Id: I105ea97f8862b5707b582904c6f2e3e9406a0f07
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/340428
Original-Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/14722
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-05-09 08:47:25 +02:00
3rdparty 3rdparty/arm-trusted-firmware: update to current master 2016-05-09 06:50:07 +02:00
Documentation Documentation: x86 MTRR setup, TempRamExit and MTRR loading 2016-03-21 20:12:35 +01:00
payloads libpayload/arm64: Mark existing framebuffer as DMAable 2016-05-09 08:30:56 +02:00
src google/gru: Determine Board ID based on the input voltage of ADC1 2016-05-09 08:47:25 +02:00
util util/sconfig: Fix warnings 2016-05-08 21:37:36 +02:00
.clang-format
.gitignore .gitignore: add build and libpayload dirs for nvramcui payload 2016-05-03 04:16:45 +02:00
.gitmodules git modules: rename git submodules to avoid hierarchies 2016-02-11 20:55:55 +01:00
.gitreview
COPYING
MAINTAINERS MAINTAINERS: Add maintainer for Pineview & x4x chipsets & boards 2016-04-19 19:25:59 +02:00
Makefile Makefile: Update payload clean targets 2016-03-09 17:01:56 +01:00
Makefile.inc xip: Do not pass --xip for early stages if CAR supports code execution 2016-05-09 05:01:58 +02:00
README
toolchain.inc toolchain.inc: test IASL by version string instead of number 2016-03-04 16:36:25 +01:00

README

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See http://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * http://www.coreboot.org/Supported_Motherboards
 * http://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult http://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see http://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  http://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  http://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.