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Duncan Laurie 93bbd41ea8 soc/intel: Enable ACPI DBG2 table generation
Enable the ACPI DBG2 table generation for Intel boards.  This is
a Microsoft defined ACPI extension that allows an OS to know what
the debug port is on a system when it is not enabled by the
firmware, so it does not show up in the coreboot tables and
cannot be easily found by a payload.

broadwell: Use byte access device, set up only when enabled since
it relies on the port being put in byte access mode and using
this serial port for debug was not standard in this generation.

skylake: Enable for the configured debug port.  Skylake uses
intelblocks for UART but not ACPI.

common: Enable for the configured debug port.  This affects
apollolake and cannonlake.

Tested by compiling for apollolake/broadwell, tested by reading
the DBG2 ACPI table on kabylake board and using IASL to dump:

    [000h 0000   4]                    Signature : "DBG2"
    [004h 0004   4]                 Table Length : 00000061
    [008h 0008   1]                     Revision : 00
    [009h 0009   1]                     Checksum : 3B
    [00Ah 0010   6]                       Oem ID : "CORE  "
    [010h 0016   8]                 Oem Table ID : "COREBOOT"
    [018h 0024   4]                 Oem Revision : 00000000
    [01Ch 0028   4]              Asl Compiler ID : "CORE"
    [020h 0032   4]        Asl Compiler Revision : 00000000

    [024h 0036   4]                  Info Offset : 0000002C
    [028h 0040   4]                   Info Count : 00000001

    [02Ch 0044   1]                     Revision : 00
    [02Dh 0045   2]                       Length : 0035
    [02Fh 0047   1]               Register Count : 01
    [030h 0048   2]              Namepath Length : 000F
    [032h 0050   2]              Namepath Offset : 0026
    [034h 0052   2]              OEM Data Length : 0000
    [036h 0054   2]              OEM Data Offset : 0000
    [038h 0056   2]                    Port Type : 8000
    [03Ah 0058   2]                 Port Subtype : 0000
    [03Ch 0060   2]                     Reserved : 0000
    [03Eh 0062   2]          Base Address Offset : 0016
    [040h 0064   2]          Address Size Offset : 0022

    [042h 0066  12]        Base Address Register : [Generic Address Structure]
    [042h 0066   1]                     Space ID : 00 [SystemMemory]
    [043h 0067   1]                    Bit Width : 00
    [044h 0068   1]                   Bit Offset : 00
    [045h 0069   1]         Encoded Access Width : 03 [DWord Access:32]
    [046h 0070   8]                      Address : 00000000FE034000

    [04Eh 0078   4]                 Address Size : 00001000

    [052h 0082  15]                     Namepath : "\_SB.PCI0.UAR2"

Change-Id: If34a3d2252896e0b0f762136760ab981afc12a2f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/22453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-11-15 16:07:21 +00:00
3rdparty 3rdparty/lib{hwbase,gfxinit}: Update to latest master 2017-10-28 19:46:17 +00:00
configs configs: Add intel/harcuvar FSP 2.0 sample configuration 2017-10-04 02:56:33 +00:00
Documentation Documentation/Intel/vboot: Remove double word *after* 2017-11-14 15:27:46 +00:00
payloads payloads/seabios: Update stable from 1.10.2 to 1.10.3 2017-11-08 15:25:19 +00:00
src soc/intel: Enable ACPI DBG2 table generation 2017-11-15 16:07:21 +00:00
util util/inteltool: Add Skylake definition to MCHBAR reading 2017-11-08 11:42:45 +00:00
.checkpatch.conf .checkpatch.conf: Ignore CORRUPTED_PATCH lint 2017-10-29 10:11:58 +00:00
.clang-format Provide coreboot coding style formalisation file for clang-format 2015-11-10 00:49:03 +01:00
.gitignore .gitignore: Do not track util/cbfstool/cbfs-compression-tool 2017-11-03 15:20:40 +00:00
.gitmodules Set up 3rdparty/libgfxinit 2016-10-29 01:35:03 +02:00
.gitreview
COPYING
gnat.adc gnat.adc: Do not generate assertion code for Refined_Post 2016-10-29 01:33:31 +02:00
MAINTAINERS MAINTAINERS: add maintainers for all PC Engines mainboards 2017-10-31 15:45:53 +00:00
Makefile build system: Deal with wildcard in subdirs-y 2017-10-29 08:48:54 +00:00
Makefile.inc Makefile.inc: Cosmetics: Format blobtool commands similar to other tools 2017-11-07 04:45:14 +00:00
README README: Update requirements 2017-06-27 17:04:32 +00:00
toolchain.inc toolchain: Always use GCC for Ada sources 2017-09-23 10:57:40 +00:00

-------------------------------------------------------------------------------
coreboot README
-------------------------------------------------------------------------------

coreboot is a Free Software project aimed at replacing the proprietary BIOS
(firmware) found in most computers.  coreboot performs a little bit of
hardware initialization and then executes additional boot logic, called a
payload.

With the separation of hardware initialization and later boot logic,
coreboot can scale from specialized applications that run directly
firmware, run operating systems in flash, load custom
bootloaders, or implement firmware standards, like PC BIOS services or
UEFI. This allows for systems to only include the features necessary
in the target application, reducing the amount of code and flash space
required.

coreboot was formerly known as LinuxBIOS.


Payloads
--------

After the basic initialization of the hardware has been performed, any
desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.


Supported Hardware
------------------

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

 * https://www.coreboot.org/Supported_Motherboards
 * https://www.coreboot.org/Supported_Chipsets_and_Devices


Build Requirements
------------------

 * make
 * gcc / g++
   Because Linux distribution compilers tend to use lots of patches. coreboot
   does lots of "unusual" things in its build system, some of which break due
   to those patches, sometimes by gcc aborting, sometimes - and that's worse -
   by generating broken object code.
   Two options: use our toolchain (eg. make crosstools-i386) or enable the
   ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this
   case).
 * iasl (for targets with ACPI support)
 * pkg-config
 * libssl-dev (openssl)

Optional:

 * doxygen (for generating/viewing documentation)
 * gdb (for better debugging facilities on some targets)
 * ncurses (for 'make menuconfig' and 'make nconfig')
 * flex and bison (for regenerating parsers)


Building coreboot
-----------------

Please consult https://www.coreboot.org/Build_HOWTO for details.


Testing coreboot Without Modifying Your Hardware
------------------------------------------------

If you want to test coreboot without any risks before you really decide
to use it on your hardware, you can use the QEMU system emulator to run
coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.


Website and Mailing List
------------------------

Further details on the project, a FAQ, many HOWTOs, news, development
guidelines and more can be found on the coreboot website:

  https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

  https://www.coreboot.org/Mailinglist


Copyright and License
---------------------

The copyright on coreboot is owned by quite a large number of individual
developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL).
Some files are licensed under the "GPL (version 2, or any later version)",
and some files are licensed under the "GPL, version 2". For some parts, which
were derived from other projects, other (GPL-compatible) licenses may apply.
Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.