4b2464fc90
All x86 chipsets and SoCs have the HPET MMIO base address at 0xfed00000, so define this once in arch/x86 and include this wherever needed. The old AMD AGESA code in vendorcode that has its own definition is left unchanged, but sb/amd/cimx/sb800/cfg.c is changed to use the new common definition. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc624051cc6c0f125fa154e826cfbeaf41b4de83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
30 lines
978 B
C
30 lines
978 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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#include <arch/hpet.h>
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#include <device/pci_ops.h>
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#include <device/pci_def.h>
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#include <soc/pci_devs.h>
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#include <soc/northbridge.h>
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#include <soc/southbridge.h>
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#include <amdblocks/psp.h>
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void soc_enable_psp_early(void)
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{
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u32 base, limit;
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u16 cmd;
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/* Open a posted hole from 0x80000000 : 0xfed00000-1 */
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base = (0x80000000 >> 8) | MMIO_WE | MMIO_RE;
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limit = (ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_LIMIT0_LO, limit);
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pci_write_config32(SOC_ADDR_DEV, D18F1_MMIO_BASE0_LO, base);
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/* Preload a value into BAR and enable it */
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pci_write_config32(SOC_PSP_DEV, PSP_MAILBOX_BAR, PSP_MAILBOX_BAR3_BASE);
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pci_write_config32(SOC_PSP_DEV, PSP_BAR_ENABLES, PSP_MAILBOX_BAR_EN);
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/* Enable memory access and master */
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cmd = pci_read_config16(SOC_PSP_DEV, PCI_COMMAND);
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cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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pci_write_config16(SOC_PSP_DEV, PCI_COMMAND, cmd);
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};
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