85 lines
2.8 KiB
C
85 lines
2.8 KiB
C
/*
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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* Copyright (C) 2009 coresystems GmbH
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <libpayload-config.h>
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#include <libpayload.h>
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#include <coreboot_tables.h>
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/*
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* Some of this is x86 specific, and the rest of it is generic. Right now,
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* since we only support x86, we'll avoid trying to make lots of infrastructure
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* we don't need. If in the future, we want to use coreboot on some other
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* architecture, then take out the generic parsing code and move it elsewhere.
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*/
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/* === Parsing code === */
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/* This is the generic parsing code. */
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static void cb_parse_x86_rom_var_mtrr(void *ptr, struct sysinfo_t *info)
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{
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struct cb_x86_rom_mtrr *rom_mtrr = ptr;
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info->x86_rom_var_mtrr_index = rom_mtrr->index;
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}
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static void cb_parse_mrc_cache(void *ptr, struct sysinfo_t *info)
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{
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info->mrc_cache = get_cbmem_addr(ptr);
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}
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int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info)
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{
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switch(rec->tag) {
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case CB_TAG_X86_ROM_MTRR:
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cb_parse_x86_rom_var_mtrr(rec, info);
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break;
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case CB_TAG_MRC_CACHE:
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cb_parse_mrc_cache(rec, info);
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break;
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default:
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return 0;
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}
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return 1;
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}
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int get_coreboot_info(struct sysinfo_t *info)
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{
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int ret;
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/* Ensure the variable range MTRR index covering the ROM is set to
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* an invalid value. */
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info->x86_rom_var_mtrr_index = -1;
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ret = cb_parse_header(phys_to_virt(0x00000000), 0x1000, info);
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if (ret)
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ret = cb_parse_header(phys_to_virt(0x000f0000), 0x1000, info);
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return ret;
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}
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