a73b93157f
It encourages users from writing to the FSF without giving an address. Linux also prefers to drop that and their checkpatch.pl (that we imported) looks out for that. This is the result of util/scripts/no-fsf-addresses.sh with no further editing. Change-Id: Ie96faea295fe001911d77dbc51e9a6789558fbd6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/11888 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
149 lines
4 KiB
C
149 lines
4 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <arch/ioapic.h>
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#include <console/console.h>
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#include <cpu/x86/lapic.h>
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u32 io_apic_read(void *ioapic_base, u32 reg)
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{
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write32(ioapic_base, reg);
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return read32(ioapic_base + 0x10);
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}
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void io_apic_write(void *ioapic_base, u32 reg, u32 value)
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{
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write32(ioapic_base, reg);
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write32(ioapic_base + 0x10, value);
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}
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static int ioapic_interrupt_count(void *ioapic_base)
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{
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/* Read the available number of interrupts. */
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int ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
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if (ioapic_interrupts == 0xff)
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ioapic_interrupts = 23;
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ioapic_interrupts += 1; /* Bits 23-16 specify the maximum redirection
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entry, which is the number of interrupts
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minus 1. */
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printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
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return ioapic_interrupts;
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}
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void clear_ioapic(void *ioapic_base)
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{
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u32 low, high;
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u32 i, ioapic_interrupts;
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printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at %p\n", ioapic_base);
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ioapic_interrupts = ioapic_interrupt_count(ioapic_base);
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low = DISABLED;
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high = NONE;
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for (i = 0; i < ioapic_interrupts; i++) {
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io_apic_write(ioapic_base, i * 2 + 0x10, low);
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io_apic_write(ioapic_base, i * 2 + 0x11, high);
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printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
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i, high, low);
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}
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if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
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printk(BIOS_WARNING, "IOAPIC not responding.\n");
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return;
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}
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}
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void set_ioapic_id(void *ioapic_base, u8 ioapic_id)
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{
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u32 bsp_lapicid = lapicid();
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int i;
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printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n",
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ioapic_base);
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printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
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bsp_lapicid);
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if (ioapic_id) {
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printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id);
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/* Set IOAPIC ID if it has been specified. */
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io_apic_write(ioapic_base, 0x00,
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(io_apic_read(ioapic_base, 0x00) & 0xf0ffffff) |
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(ioapic_id << 24));
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}
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printk(BIOS_SPEW, "IOAPIC: Dumping registers\n");
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for (i = 0; i < 3; i++)
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printk(BIOS_SPEW, " reg 0x%04x: 0x%08x\n", i,
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io_apic_read(ioapic_base, i));
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}
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static void load_vectors(void *ioapic_base)
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{
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u32 bsp_lapicid = lapicid();
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u32 low, high;
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u32 i, ioapic_interrupts;
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ioapic_interrupts = ioapic_interrupt_count(ioapic_base);
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#if CONFIG_IOAPIC_INTERRUPTS_ON_FSB
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/*
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* For the Pentium 4 and above APICs deliver their interrupts
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* on the front side bus, enable that.
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*/
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printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n");
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io_apic_write(ioapic_base, 0x03,
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io_apic_read(ioapic_base, 0x03) | (1 << 0));
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#endif
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#if CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
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printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n");
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io_apic_write(ioapic_base, 0x03, 0);
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#endif
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/* Enable Virtual Wire Mode. */
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low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
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high = bsp_lapicid << (56 - 32);
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io_apic_write(ioapic_base, 0x10, low);
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io_apic_write(ioapic_base, 0x11, high);
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if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) {
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printk(BIOS_WARNING, "IOAPIC not responding.\n");
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return;
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}
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printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
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0, high, low);
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low = DISABLED;
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high = NONE;
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for (i = 1; i < ioapic_interrupts; i++) {
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io_apic_write(ioapic_base, i * 2 + 0x10, low);
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io_apic_write(ioapic_base, i * 2 + 0x11, high);
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printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n",
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i, high, low);
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}
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}
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void setup_ioapic(void *ioapic_base, u8 ioapic_id)
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{
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set_ioapic_id(ioapic_base, ioapic_id);
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load_vectors(ioapic_base);
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}
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